支援X86指令集架構與其單指令流多資料流擴充指令集之可重定目標混合式二元執行檔轉譯器

Abstract

二元執行檔轉譯是計算機系統虛擬化的重要技術之一，透過一連串的機器碼轉譯，來讓一個指令集架構能夠模擬另一個不同的指令集架構。傳統上，二元執行檔轉譯主要分為靜態和動態兩類形式。靜態轉譯以程式為單位轉譯，並盡可能進行全面性的最佳化。動態轉譯則是在程式執行時期同時進行直譯與轉譯，效能較差；然而由於執行時期可以取得較多的狀態資訊，因此在Code discovery (代碼探索)和 Code location (代碼定址)等諸多問題上能夠較有效率地處理。混合式二元執行檔轉譯是最近才被提出的新轉譯技術，結合了靜態轉譯及動態轉譯兩者的優勢，利用靜態轉譯產生高效能的目標程式，並且在執行時期動態連結動態轉譯系統，以處理靜態時期因資訊不足而難以解決的問題；既能在大部分情況下維持良好的程式執行效率，也能以妥善又有效的方式處理各種模擬(emulation)過程中的狀況。Intel x86是相當具有代表性的複雜指令集電腦，在伺服器、個人電腦和嵌入式平台都有相當的市占率。之前提出的混合式二元轉譯器主要是針對ARM此精簡指令集架構所設計，本研究則著重在不定長度的複雜指令集架構，對其代碼探索問題進行解決。此外，隨著多媒體應用程式需求的增加，越來越多的處理器架構採用SIMD (單指令流多資料流) 擴充指令集來支援平行化運算的需求。綜上所述，此篇論文以LLVM編譯器框架為基礎實作一個為x86及其SIMD擴充指令集設計的混合式二元執行檔轉譯系統。實驗結果顯示，本研究實作之轉譯器在轉譯Auto-vectorized EEMBC benchmarks上之效能平均較QEMU快3.41倍。

In this thesis, we present a hybrid binary translation (HBT) system which supports Intel x86 instruction set architecture (ISA) and its SSE2 extension based on LLVM. HBT is a binary translation technology developed recently which combines the merits of both static binary translation (SBT) and dynamic binary translation (DBT) and provides better performance and code-generation quality compared to a pure DBT. In addition, it does not suffer from the code location and code discovery problems caused by indirect branches that cannot be handled easily by SBT, especially on those complicate ISAs such as Intel x86. Moreover, Single-Instruction-Multiple-Data (SIMD) parallel computing have been studied for decades and included in most of the modern general-purpose CPU designs. Early works of retargetable SIMD extension binary translation focused on DBT. The HBT system proposed in this thesis may emulate SIMD instructions with vectorized retargetalbe LLVM Intermediate Representation (IR) and generate fully optimized target code statically with high performance to take full advantages of target SIMD instructions if provided in target. The experimental results show the execution time of that auto-vectorized EEMBC benchmarks translated by our translator is 3.41 times faster than that by QEMU in average.