垂直式(110)及(551)矽晶面環繞式閘極金氧半場效應電晶體之特性研究

Abstract

近年來，電晶體根據摩爾定律持續微縮，但由於微影技術之限制，10奈米以下微縮正面臨巨大挑戰，如元件結構設計，主動層材料選擇，介面品質好壞，寄生電容，及接觸電阻等，尤其在14 奈米技術節點以下的製造與應用更加受到關注及研究。繼三閘極電晶體之後，環繞式閘極奈米線由於其優異的閘極控制，積體電路佈局占地大幅降低，速度提升，及低功率消耗等優點，使其成為新世代電晶體元件之熱門人選。近期許多關於環繞式閘極奈米線在矽與三五元素之研究，但以矽為基底之環繞式閘極奈米線電晶體，因電洞遷移率(hole mobility)較低於電子的遷移率(electron mobility)，P型電晶體的效能比N型來得差。在本論文中，根據指導教授提出，（100）晶板上蝕刻Fin具有(551) 面且向<100>傳導的矽晶面，如果垂直的Fin表面平滑，即有較低的表面粗糙度，就可得N型與P型效能相襯(Balanced)矽基底電晶體特性。 在本論文中，將以模擬探討(551)矽晶面三維垂直式環繞式閘極奈米線的特性研究。(551)矽晶面垂直式環繞式閘極奈米線電晶體展現其優於一般電晶體之效能表現，其中垂直式奈米線能使佈局密度提高並仍能維持其效能，且(551)矽晶面具有較好之特性表現，可為繼平面式電晶體、三閘極電晶體後，新世代電晶體元件繼起之秀。

Scaling beyond Moore’s Law has faced a big challenge due to the lithography limitation beyond the 10nm node. Several issues, such as device structures, channel materials, interface quality, capacitance and contact resistance, have been studied for beyond 14 nm logic applications. Nanowire gate-all-around (GAA) structures are promising candidates due to their high gate-controlled ability, layout area reduction, speed improvement and low power consumption, and have been investigated and applied to Si or III-V based MOSFETs to enable further scaling. Si-based GAA nanowire FETs reported so far didn’t show the “balanced” performance, which means the hole mobility is still quite lower than electron mobility. However, T. Ohmi et. al. have reported a performance balanced CMOS on Si-based MOSFET and excellent surface stability by using Si (551) orientated substrate.. In this thesis, 3D GAA vertical Si (551) Fin type MOSFET transport to <100> direction on (100) Substrate have been proposed by professor Chang and simulated to study the basic device and circuit electrical characteristics.