氮氧化鉿電荷捕獲層與二氧化鉿/二氧化矽雙層結構於非揮發性記憶體之特性研究

Abstract

近年來，隨著消費性及可攜式電子產品的蓬勃發展，例如手機/相機記憶卡和隨身碟等，非揮發性記憶體元件的市場成長相當快速。且由於這些非揮發性記 憶體元件擁有高密度、快速的抹寫速度、良好的資料保存力及資料耐久性等特性，故其受到相當大地重視。 然而，當快閃記憶體(Flash memory)元件進入20奈米技術時，傳統多晶矽(poly-Si)懸浮閘(Floating-Gate)快閃記憶體將會面臨因壓力所引起的漏電流(SILC)而造成電子的流失及元件間的耦合等一連串的挑戰。當穿隧氧化層厚度微縮時，因壓力所引起的漏電流將會造成儲存資料經由單一缺陷而大量流失；且多晶矽會造成相鄰元件間寄生電容的產生，使得電子在元件間產生游移，造成資料保存性(Retention)以及耐久度(Endurance)等可靠度大幅降低。因此提出具有分離性的電荷捕獲及元件間不耦合等特性的電荷捕獲快閃記憶體(Charge-Trapping Flash)元件取代傳統懸浮閘快閃記憶體。而未來元件縮小的同時，因應元件低電壓操作及高可靠度的元件需求，我們將專注於高介電係數材料堆疊電荷捕獲快閃記憶體的研究。且藉由高介電材料的應用及能帶工程(Band Engineering)的概念，提出一個元件特性更佳的閘極堆疊電荷捕獲快閃記憶體結構。 在此論文中，我們提出一利用氮氧化鉿(HfON)電荷捕獲層以及HfO2(二氧化鉿)/SiO2(二氧化矽)雙層穿隧/阻擋氧化層的金屬-氧化層-氮化層-氧化層-矽(MONOS) 元件結構。而此元件具有於100毫秒和電壓 ±18伏特的操作條件下，具有4.7伏特的初始資料記憶視窗、室溫下經過104秒後仍具有3.4伏特的記憶視窗，以及耐久性於104次的寫入/抹除後還保有4.2伏特記憶視窗等良好的非揮發性記憶體特性。

With the developments of consumer and portable electronic devices, such as cellular phones, cameras memory cards, the nonvolatile memory (NVM) market grows rapidly recently. The NVM devices with high density, fast program/erase speed, good endurance and data retention have been attracted much attention. Have beenHowever, with flash memory entering 20nm technology node, the conventional poly-silicon floating gate (FG) flash memory faces serious challenges from stress-induced leakage current (SILC) -induced charge loss and cell-to-cell coupling. When the thickness of the tunneling oxide decreases, the SILC can discharge the whole FG via even one single defect. Moreover, traditional poly-silicon FG can cause the adjacent parasitic capacitance and make the electrons move freely between the components, and thus significantly reduce the device reliability, such as data retention and endurance. As a technology breakthrough, charge trapping flash (CTF) memory is proposed to replace the traditional FG flash memory due to its localized charge storage and coupling-free structure. With the demands for low voltage and high reliability in further scaling down, this work focused on the research on novel CTF devices with stacked high-k structures. By introducing high-k dielectrics and the concept of band engineering, we proposed novel gate stack structures for future CTF application to improve the characteristics of CTF devices. In this thesis, we proposed an improved metal/oxide/nitride/oxide/Si-substrate (MONOS) structure with a high-k HfON as trapping layer and HfO2/SiO2 barrier as double tunneling and blocking layers. The good memory performances were obtained, including a 4.7 V initial memory window, a 3.4 V retention window after 104 seconds at 25℃, and a 4.2 V endurance window after 104 cycles under ± 18 V program/erase (P/E) for 100 ms, showing a strong potential in high-performance non-volatile memory application.