具備 0g 校正之 CMOS/MEMS 加速度計單晶片設計

Abstract

本論文在標準 0.18 μm CMOS 電路製程下完成一具備 0g 校正之 CMOS/MEMS 加速度計單晶片設計。採用低雜訊截波穩定式架構與望遠鏡式放大器來達成低雜訊，輸出雜訊在 1KHz 為 26.85 μg/√Hz 。搭載數位校正電路以補償感測器介面電路端之偏移，最大可補償 21 fF 之偏移。模擬結果顯示系統具靈敏度為 452.1 mV/g ，功率消耗約為 1.16 mW 。

A monolithic accelerometer design with zero-g calibration in standard 0.18 μm CMOS mixed signal ASIC process is presented. The low noise chopper architecture and telescopic topology are adopted to achieve low noise. The output noise is 26.85 μg/√Hz at 1KHz. On-chip digital offset calibration enables compensation of random offset in the sensor interface. The maximum 21 fF capacitance mismatch can be calibrated. The simulation results show that the whole system have 452.1 mV/g sensitivity. The power consumption is about 1.16 mW.