設計一個應用於Class D的三角積分轉換器

Abstract

本論文主要是設計一個應用於Class D的三角積分轉換器，內部包含一個升頻濾波器以及一個五階三角積分調變器，其整體系統的輸入訊號為16位元，輸出訊號為1位元，取樣頻率為8K Hz，訊號頻寬為4KHz。

升頻濾波器的功能為提昇輸入取樣頻率和衰減升頻後產生的映像(image)，它是由多級升頻濾波器串接而成，其中包含兩級的FIR與一級的CIC濾波器，三角積分調變器的功能主要是可以將輸入訊號調變成數位訊號，且輸出的訊號可以得到很高的訊號雜訊比(signal to noise ratio)。

整個系統主要以Verilog硬體描述語言實現電路，最後以FPGA驗證，在超取樣率(oversampling ratio)為64的條件下，SNR可以到達96dB，預期未來能將其輸出級直接驅動H bridge，以實現高效率、高效能的D類放大器。

This thesis proposes a design of delta-sigma converter for application of class D, which consists of an interpolator filter (IF) and a fifth-order delta-sigma modulation (DSM). The system input is 16-bit with a 1-bit ouput. The sampling rate is 8 KHz with one 4 KHz signal bandwidth.

The interpolator filter, which is used to eliminate the unwanted upsampling image, contains two cascaded finite-impulse-response (FIR) and 1-stage CIC filter. The DSM is a method to encode input signals into digital signals and to provide high signal to noise ratio (SNR) for output signals.

The test circuit is designed and implemented by Verilog and FPGA, respectively. The experimental SNR is higher than 96dB when the oversampling ratio (OSR) is 64, the output of high resolution will be able to drive the H-bridge in the future, and realize a class D amplifier with high efficiency and high performance.