P型SONOS快閃記憶體電荷注入均勻性與效率之研究

Abstract

本篇論文主要研究P型SONOS快閃記憶體電荷注入氮化矽（SiN）層的均勻性與注入效率的改善。吾人採用寫入記憶體的方法為動態寫入（Dynamic Program），而其寫入機制為通道熱電動誘發熱電子注入（Channel Hot Hole Induced Hot Electron injection, CHHIHE）。利用簡單的量測方法，也就是正向讀取（Forward Read, FR）與反向讀取（Reverse Read, RR），來監測記憶體在寫入過程時的電荷均勻程度。電荷的均勻性與注入效率會取決於動態寫入時，施加在閘極（control gate）的脈沖寬度（pulse width, Vpw）、脈衝高度（pulse height, Vph）以及脈衝的數量（number of Vstep）。當脈沖寬度與脈衝的數量增加時，注入氮化矽層的電荷會變得更為均勻。而調整脈衝高度可以使注入效率得到改善，這是由於記憶體的臨界電壓會在寫入過程中上升，隨著時間調整脈衝高度，可以讓閘極偏壓跟隨臨界電壓的上升而上升，使寫入過程保持在最佳的注入效率。因此，最佳的寫入電壓，可以藉由控制脈沖寬度（pulse width, Vpw）與脈衝高度（pulse height, Vph）來得到。

In this thesis, we investigate the trapped charge uniformity in SiN layer and the improvement of charge injection efficiency by using dynamic programming (PGM) scheme of Channel Hot Hole Induced Hot Electron injection (CHHIHE) in p-channel SONOS memory device. By utilizing simple measurement technique (i.e., the measure of Forward/Reverse PGM windows), monitor the trapped charge uniformity in SiN layer at different PGM windows. The trapped charge uniformity and the charge injection efficiency are strongly dependent on dynamic pulse width (Vpw), pulse height (Vph) and number of Vstep, which is applied to control gate. The trapped charge becomes more uniform in SiN layer as increasing Vpw and number of Vstep. Besides, the PGM efficiency can be improved by modulating Vph, by changing PGM bias dynamically increasing to trace the threshold voltage (Vth) of memory cell during PGM. Therefore, the optimization of injected charge state can be achieved by adjusting Vpw and Vph.