奈米結構雙塊高分子層在非揮發有機場效電晶體記憶體元件中影響了記憶體特性與并五環分子之堆疊

Abstract

本篇論文主要探討以雙塊式高分子 (diblock copolymer, PS56k-b-P4VP8k) 作為非揮發性有機場效應電晶體記憶體之電荷儲存層時，（具有 P4VP-core, PS-shell) 微胞奈米結構厚度對於記憶體寛度以及電洞遷移率之影響，並以原子力顯微鏡，同步輻射光源探討該層和電子通道層之奈米結構，分析其與記憶體性質之間的關係。 例如，當 PS56k-b-P4VP8k 層厚度連續從 60 nm 改變至 27 nm 時，記憶體寛度從 7.8 V 改變至 21 V，增加為原來的 2.5 倍。使用同步輻射光源低掠角小角X光散射 (GISAXS) 與低掠角廣角X光散射 (GIWAXS) 分別去探測奈米結構微胞的 PS56k-b-P4VP8k 與直接定位在 PS56k-b-P4VP8k 層頂端之并五環 (Pentacene) 分子的堆疊。利用此方式，我們能夠去破解這雙層結構之特性與連接它們的效應在具有類似結構元件之記憶成果。藉由 GISAXS 與 GIWAXS 可觀察到在 PS56k-b-P4VP8k 層中，微胞與微胞之間的距離與橫向排列方式會隨著 PS-shell 的厚度而有所改變，當厚度增加時，PS-shell 在橫向距離減少，使得記憶體的開閥電壓偏移量受到影響。再者，發現在 PS56k-b-P4VP8k 層上作為電子通道層的并五環(Pentacene) 會受到 PS56k-b-P4VP8k 層之結構而影響其分子堆疊方向以及晶粒大小，進一步影響電洞遷移率。這些結果顯示出，要調整記憶體中寛度以及電洞遷移率，改變電荷儲存層中雙塊式高分子薄膜厚度和微胞奈米結構會是個簡單且有效的方式。

Organic field-effect transistor (OFET) memory devices incorporating the copolymer polystyrene-block-poly(4-vinylpyridine) (PS56k-b-P4VP8k) layer, which features a thickness-dependent micellar nanostructure (P4VP-core, PS-shell), as a charge trapping layer can exhibit tunable memory windows for p-channel applications. For instance, the memory window increased substantially from 7.8 V for the device incorporating a 60 nm thick PS56k-b-P4VP8k layer to 21 V for the device incorporating a 27 nm thick layer, an increase of more than 2.5 times. Using simultaneous synchrotron grazing-incidence small-angle X-ray scattering and wide-angle X-ray scattering to probe the nanostructured micellar PS56k-b-P4VP8k layer and the pentacene layer positioned directly on the top of the copolymer layers, respectively, we were able to elucidate the structural characteristics of the bilayer and to correlate their effects with the memory performances of devices with similar architectures. For the PS56k-b-P4VP8k layers, we found that the inter-micelle distance and their lateral arrangements depended on the layer thickness: the thickness of the PS shells in the lateral direction decreased upon increasing the layer thickness, as did the memory window for the OFET device that incorporated the PS56k-b-P4VP8k layers, showing a strong dependence of the threshold voltage shifts (i.e., memory window) on the distance between the micelles. Additionally, for the molecular packing of the pentacene layer positioned on the copolymer layer, we found that the PS56k-b-P4VP8k layers affected not only the orientation of the pentacene molecules but also their grain sizes, thereby affecting the hole mobility of the memory devices. These results suggest that tuning the micellar nanostructure of the block copolymer thin film that was used as a trapping layer can be a simple and effective way for optimizing the memory window and affecting the hole mobility of OFET memory devices.