應用於超高效率H.265標準之高記憶體效率內嵌視訊解碼器

Abstract

在現今產品裏，電路的趨勢為規模越龐大和複雜，把所有的功能整合在一顆IC當中，便可以使產品輕薄短小甚至是可用於可攜式且具有吸引力的裝置。而當今火紅的應用產品裏頭的視訊壓縮解碼器已從H.264/AVC演進到最新一代High Efficiency Video Coding/H.265，高效率的壓縮演算帶來高效能壓縮卻造成硬體實現上的困難。這些困難，包含了硬體的成本，功率的消耗。在視訊解碼器的記憶體裡，其中的模組包括內嵌預測器(Intra Predictor)、去區塊濾波器(De-blocking Filter)佔了總內部記憶體83%。因此，此作品提出了共享記憶體和記憶體階層兩種方法，實現了低功率低記憶體的內嵌視訊解碼器，改善了記憶體空間，並且具有架構可調整之特色，可支援最新一代影像壓縮編碼HEVC/H.265，使其能夠降低整合的整本，及外部記憶體搬移功率消耗。以視訊解碼器細部來說，我們整合了三個演算模組，內嵌預測器(Intra Predictor)，轉換器(Transform Coder)，去區塊濾波器(De-blocking Filter)搭配記憶體共享，試圖降低記憶體空間，另外更以”預測”的方法利用記憶體階層來實現改善記憶體頻寬，更可以減少記憶體空間需求，提高預測率，可以高達60%的記憶體節省效率，且可減少記憶體核心功率至19%，以達到低成本低功率的需求。除此之外，內嵌視訊解碼器利用的波前平行處理，達到最高吞吐量8Kx4K@30fps。最後此硬體在以Socle-tech Cheetah Design Kit (CDK)搭配外部記憶體(SDRAM)和CPU的協同合作，能夠在LCD螢幕上播放出正確結果。

In today’s product, the trend of the circuit is becoming large and complex, to integrate the functionality in an integrated circuit will make the product more portable and more attractive. Nowadays, the video decoder has been revolved from H.264/AVC to High Efficiency Video Coding (HEVC), high efficient compression algorithm brought the better performance but has poor impact on the hardware implementation in the video codec. These conflicts including the hardware cost, power consumption are poor to the chip performance. In the memory requirement, the intra predictor and deblocking filter are occupying almost 83% in the video decoder. As a result, the thesis has proposed line buffer sharing and memory hierarchy methods, and has implemented the low power and low memory requirement I frame decoder. The architecture is reconfigurable, low memory cost and can support the newest video standard HEVC/H.265. Detail speaking, we integrate the intra predictor, transform coder and in-loop filter with proposed memory reduction algorithm, attempting to reduce the memory requirements. We also used memory hierarchy with prediction-based method to enhance the hit rate and lower down the power consumption. Both the line buffer sharing and memory hierarchy methods can achieve the 60% memory reduction ratio with 19% memory core power reduction for the low cost and low power application. Besides, the hardware has been designed using wavefront parallel processing to achieve super-high vision throughput 8Kx4K. Further, the I frame decoder is verified co-design with FPGA platform using Socle-tech Cheetah Design Kit (CDK) with SDRAM and CPU, and the results could be shown on the LCD panel.