低功耗前瞻靜態隨機記憶體之測試方法與錯誤模型

Abstract

對於新開發的低功耗和前瞻靜態隨機存記憶體(SRAM)，製造缺陷在其上所造成的錯誤行為往往比對於在傳統SRAM上造成之錯誤行為來說較為複雜。在相關的研究並未被充分的討論的情況下，許多針對傳統6T SRAM之一般性的測試方式都未被驗證，也因此無法滿足對於在製造與設計堅固和可靠的低功耗SRAM與未來的製程技術配合的測試需要。在這篇論文中，我討論了對於各種已在科技文獻中發表的低功耗SRAM設計的測試。針對不同的記憶胞結構我進行了分類並分析相對應的錯誤行為，並開發至少四個可以處理的不同的低功耗SRAM測試需要的測試方法。除了討論各種記憶胞結構，我也延伸了從傳統的平面CMOS元件的討論，到目前極具前瞻性的FinFET元件，以及特殊的薄膜電晶體元件。對於該些前瞻的SRAM，我進行了元件等級的TCAD模擬、SPICE模型提取和針對多晶矽通道模型建立之應用等，以進行驗證所提出的測試方法與最佳化前瞻SRAM設計的相關參數。

For the new-developed low-power and advanced SRAMs, the fault behaviors due to manufacture defects are often relatively complicated when being compared to the traditional 6T SRAM. And the complete analysis has not been fully discussed. As a result, the test effectiveness of conventional test methods for the 6T SRAM may not satisfy the need for producing robust and reliable low-power SRAMs with future technologies. In this thesis, I have discussed the testing of various low-power SRAM designs which have been published in literatures. By categorizing the different cell structures and analyzing the corresponding faulty behaviors, I have developed at least four new test methods which can deal with the diverse needs of the low-power SRAM testing. In addition to including the various cell structures, I also extend the discussion to the SRAM which comes with the specific peripheral write-assist circuitry. For the data-aware write-assist SRAM, a high-fault-coverage and time-efficient test method is proposed. Finally, the discussions of the special Gate-Oxide Short defects at the traditional planar bulk CMOS and the promising FinFET technology are also covered. For those advanced SRAMs, device-level TCAD simulation, SPICE model extraction, and circuit-level defect model establishing were proceeded to either verify the proposed test methods or to achieve high yield optimized advanced SRAM designing.