Data Pattern對NAND快閃記憶體寫入擾動特性之研究

Abstract

本篇論文主要透過完整數值計算與元件模擬來研究資料模式對NAND快閃記憶體寫入擾動特性之影響。研究結果發現，寫入擾動的程度主要由未選擇記憶體元件的Pass-Gate voltage和NAND string上的資料模式所決定。因此需要同時考慮氧化層垂直電場與鄰近記憶體元件的水平電場效應。46nm 尺寸2Gbit 大小NAND快閃記憶體量測資料與模擬結果作比對來探討寫入擾動特性之影響。從結果來看11101是最差的data pattern。因為“0”的低截止電壓使得位能障降低，電子能從鄰近的記憶體元件越過此位能障到達選擇的記憶體元件並造成通道的電位下降。本論文研究結果機制也可以應用在三維度(3D) NAND，並可為未來元件開發作為重要的參考價值。

This thesis investigates the complete numerical model of the NAND Flash program disturbance phenomena which have strong dependence of the data pattern in the NAND cell string. The program disturbance is mainly determined by two factors, such as pass-gate voltage of unselected cells and the string data pattern. This characteristic is also determined by both the probability of the electron energy gain due to the lateral electric field between the neighboring cell and program disturbance cell as well as the gate oxide field. 2Gbit 46nm rule NAND Flash was used to measure and is compared with simulation results. From the result show that data pattern 11101 exhibit the worst case. Because the current come from low Vt of “0” neighboring cell would induce the barrier lowering, thereby causing the channel potential of the selected cell to drop. Moreover, this phenomenon is independent from design rule and also will occur in 3D-NAND Flash. Thus, this model can draw the projections on future NAND technologies.