标题: 针对安全性嵌入式系统之弹性管线化设计与实做
Design and Implementation of a Flexible Pipeline for Secure Embedded Systems
作者: 陈治玮
ZhiWei Chen
单智君
Jean, Jyh-Juin Shann
资讯科学与工程研究所
关键字: 可重组式电路;超大型积体电路;密码学;Reconfigurable Hardware;VLSI;Cryptography
公开日期: 2004
摘要: 在现今的环境中,提供加密的需求已是刻不容缓,如果在嵌入式系统中加入加密的运算,就会遇到几项议题,其中我们针对处理速度以及硬体弹性这两项议题进行讨论,我们针对目前较常见的加密演算法,分别为AES DES 和RSA。提供一个可在AES,DES和RSA之间弹性转换,并且可以弥补速度上不足之硬体。在考量处理速度不足这项议题之下,我们采用速度与面积乘积为评比标准。

在本论文中,我们首先分析此三演算法之运算需求,然后针对不同类型之运算分别设计出排列组合单元,运算单元以及记忆单元,其中排列组合单元采客制化设计,运算单元由处理单元所组成,记忆单元则由单位缓冲区所组成,我们讨论处理单元以及单位缓冲区的设计以及考量在不同比例之运算单元以及单位缓冲区之下,造成面积速度乘积的影响,最后所提出的设计和针对个别演算法之客制化设计做比较,比较结果显示我们的方法确实在面积速度乘积有较好的效果。
Providing security has become more and more urgent and necessary in embedded systems. If we want to support security in our embedded systems, some issues must be solved. We focus on processing gap and flexibility concerns. We target on the three commonly used cryptographic algorithms, AES, DES and RSA. In our thesis, we want to propose a hardware which solves the processing gap and switches flexibly between AES, DES, and RSA. Under the consideration of processing gap, we use space-time product as our performance metrics.

We first classify the operation of the three cryptographic algorithms into three classes. Then, we design modules for different operation classes respectively. The three modules are permutation-combination unit, computation unit and memory unit. The permutation-
combination unit is a custom design. The computation unit is consisted of processing elements and the memory unit is consisted of tile buffers. The different ratio of processing elements and tile buffers will lead to different results. We choose the most appropriate ratio. Finally, our proposed method will get better result than ASIC design.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009217516
http://hdl.handle.net/11536/73168
显示于类别:Thesis


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