標題: 週型型矽奈米柱陣列無機-有機混合型太陽能電池
Characteristics of Conductive Polymer/Silicon Heterojunction Solar Cells with Periodic Nanostructures
作者: 黃揚越
Huang, Yang-Yue
余沛慈
紀國鐘
Yu, Peichen
Chi, Gou-Chung
光電工程研究所
關鍵字: 太陽能電池;週期型矽奈米柱陣列;solar cell;periodic silicon nano rods
公開日期: 2013
摘要: 無機-有機混合型太陽能電池主打高效率、低成本,是備受期望的新型太陽能電池,但是與矽晶太陽能電池相比,其效率仍然偏低。為了進一步提升無機-有機混合型太陽能電池的效率,我們成功利用電子槍微影技術搭配反應式離子蝕刻所製造出週期型矽奈米柱陣列結構,並且利用週期型矽奈米柱陣列結構藉由簡單旋塗上高導電有機分子PEDOT:PSS製作出光電轉換效率達7.02%之異質接面無機-有機混合型太陽能電池。藉由反射率量測我們可以證明週期型矽奈米柱陣列結構具有優異的抗反射能力,以正方排列為例,其與太陽光頻譜之加權反射率可以達到16.03%,比平面矽基板少了將近一半的反射損失。當奈米柱與PEDOT:PSS緊密貼合形成核殼結構時,大面積的接面面積與較短的載子傳輸路徑有助於載子的收集與傳導, 經由計算可以發現,各個波長的內部量子效率都有5~10%的提升。由反應式離子蝕刻製作的週期型矽奈米柱陣列結構其表面有許多損壞,我們利用損壞移除蝕刻的方法降低這些表面損壞,成功回復了因為表面損壞而下降的元件效率。除此之外,我們利用二氧化鈦膠體成功對矽基板背面進行表面鈍化,藉由載子生命週期量測,我們可以證明經過二氧化鈦膠體鈍化過的表面,其載子生命週期可由15.33微秒提升至76.33微秒;藉由電性量測,我們也發現經過背表面鈍化的元件,其各波長的量子轉換效率平均有5%左右的提升。最後,我們以R-soft針對不同週期、填充率的週期型矽奈米柱陣列結構進行加權反射率模擬,發現在週期 330奈米,填充率0.25時,有最低12%的加權反射率,有利於元件效率的最佳化。
Organic-Inorganic heterojunction hybrid solar cell has the advantage of high efficiency and low cost. However, the efficiency of hybrid solar cell is still not enough compared with the silicon solar cell. In this work, we demonstrate a hybrid heterojunction solar cell based on the structure of conductive polymer PEDOT:PSS spun cast on n-type crystalline silicon nanorod (SiNR) arrays with periodic arrangements, which has 7.09% power converted efficiency The nanorod arrays are fabricated by electron beam (E-beam) lithography followed by reactive-ion etching (RIE). By reflection measurement, we demonstrate that the period silicon nanorod arrays structure exhibit an excellent light harvesting ability. For square arrangement structure for example, the weighted reflection based on solar spectrum can reach to 16.03 % which reduce almost half of the reflection loss compared to silicon plane substrate. In addition, we show that SiNRs and PEDOT:PSS can form core-shell structure that provides a large p-n junction area for carrier separation and collection , which lead to internal quantum enhance 5~10% . However, the reactive-ion etching cause a lot of surface damages on the surface of the rod which cause a lot of interface defect between Silicon and PEDOT:PSS. A post-RIE damage removal etching (DRE) is subsequently introduced in order to mitigate the surface damages issues .In addition, we successfully passivate the rear surface of the silicon substrate using titanium oxide sol-gel. By measurement, we observe that the minority carrier lifetime enhance from 15.33 us to 76.33 us after passivated by titanium oxide sol-gel. Finally, we map the weighting reflection of silicon nanorod arrays with different periods and filling ratio, which explain the reason of lowing reflection of device after DRE treatment and indicate that arrays with 330nm period and 0.25 filling ratio have the minimum weighting reflection 12%.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT070050543
http://hdl.handle.net/11536/73199
顯示於類別:畢業論文