設計利用堆疊電感製作3.1-10.6 GHz超寬頻低雜訊放大器與12-18 GHz接收機前端電路

Abstract

本論文主要由兩個部份組成， 所有的晶片均使用安捷倫ADS和Momentum軟體模擬，並且由TSMC 0.18 um mixed-signal/RF CMOS 1P6M 制程實現。 第一部份提出了一個超寬頻低雜訊放大器設計。此電路利用共源級架構和電流再利用技術，具有低功耗、低雜訊和高增益的特點。爲了減少大量電感導致晶片面積變大，提出了堆疊式立體電感并應用在電路中。電路量測的功耗在7.4 mW， 增益為14-18 dB， 最低雜訊為8 dB。 這種情況的產生可能來自於不精確的堆疊式立體電感模型和高頻時layout走線帶來的寄生電容電感效應。量測線性度比模擬好，P1dB為 -12 dBm， IIP3為-3 dBm。晶片面積為 0.54 mm2。 第二部份提出了Ku Band接收機前端電路。此電路由低雜訊放大器，被動balun和降頻器組成。低雜訊放大使用電流再利用技術減小電流損耗和更好的雜訊表現。片上的被動巴倫設計在低雜訊放大器和下混頻器之間，實現了差分訊號輸出。此巴倫是基於Marchand Balun形式，能夠達到寬頻匹配。爲了獲得更好地隔離效果，降頻器是基於Gilbert Cell架構，並且利用電容耦合和current bleeding技術來實現高增益和低雜訊。模擬的電流消耗為22.4 mW， 轉換增益為32 dB，DSB NF為4 dB。P1dB 和 IIP3 分別為 -29 dBm 和 -23 dBm。晶片面積為 1.6 mm2。

This thesis mainly contains two themes, all the simulations are performed by Agilent ADS and Momentum. The chips are all fabricated in TSMC 0.18 um mixed-signal/RF CMOS 1P6M process by CIC. Part I presents an UWB LNA. The LNA uses common source topology and current-reused technology to lower the power consumption and provide low noise. In order to decrease chip area, the stacked 3D inductors are proposed. The measured power consumption is 7.4 mW, gain is 6-12 dB over 3.1-10.6 GHz, and NF is more than 8 dB. This situation may come from incorrect on-chip model or incorrect proposed 3D inductor model. Whereas, the degraded gain leads to better linearity; the measured P1db and IIP3 are -12dBm and -3 dBm respectively. The chip area is only 0.54 mm2. Part II presents a Ku band receiver front-end circuit. The circuit consists of a LNA, a passive balun, and a down-conversion mixer. The LNA is designed by current-reused technology to lower the noise and power consumption. An on-chip passive balun is proposed between the LNA and mixer to realize differential signals, which is based on Marchand balun for wideband matching. To acquire better isolations, the gilbert cell is used for the mixer. Capacitor cross couple and current bleeding technologies are used to improve the conversion gain and lower the noise figure. The proposed front-end circuit consumes 22.4 mW, and the simulated conversion gain is 32 dB, as well as 4 dB noise figure. The P1dB and IIP3 are -29 dBm and -23 dBm respectively. The chip area is 1.6 mm2.