考量跨電源供應域靜電放電與快速帶電器件模型分析之平面規劃演算法

Abstract

當電晶體逐步的縮小，元件的可靠性上的問題變得更加重要。更小的電晶體，因此有更薄的電晶體管閘極氧化層，這意味這電晶體更容易在靜電放電(ESD)的事件受傷害。在三個ESD模型之中，由於帶電器件模型(CDM)其更快和更大的放電電流，導致災難性損壞的可能性較大。其他兩個ESD模型，人體模型(HBM)和機器模型(MM)，所導致的損壞可以有效地在元件階段被保護。但是，因為CDM事件的不可預測性，保護對CDM的事件是更複雜的，雖然以前的研究在元件階段上實施ESD保護方法，我們提出了一種高效和有效的方法，在設計階段能夠防止CDM事件。當佈局規劃是確定的，我們提出了一個根據聚集分析的電源箝位器擺放演算法去擺放電源箝位器在優越的位置，能有效減少電源箝位器的數量，同時達到比常規方法更好的保護。

The issue on reliability of the device becomes more critical as transistor progressively scales down. Smaller transistor and hence thinner gate oxide implies transistors are more vulnerable against an Electrostatic Discharge (ESD) event. Among the three models in ESD, Charged Device Model (CDM) has the greater potential to deal catastrophic damage to the device due to its faster and larger discharging current. Damage induced from the other two ESD models, human body model (HBM) and machine model (MM) can be effectively protected at device stage. However, protection against a CDM event is much more sophisticated due to its unpredictability. While most previous works on ESD protection methodology are implemented at device stage, we propose an efficient and effective methodology to protect against a CDM event at design stage. When floorplan of a design is determined, we propose a power clamp placement algorithm derived from clustering analysis to place power clamp at strategic location which can effectively minimize number of power clamps while achieving better protection compared to conventional method.