新穎垂直通道無接面薄膜電晶體之模擬研究

Abstract

本論文主要是針對垂直通道無接面薄膜電晶體的電性作模擬探討。首先我們先以製程模擬的方式建立元件結構：以等向性沉積方式製作出多晶矽的垂直通道，並以臨場摻雜的方式摻入磷離子。依據元件基本特性變更其通道厚度、摻雜磷離子濃度、偏置深度以及通道的長度找出該尺寸的最佳參數調控值。根據本篇研究發現當元件的通道厚度設計為10 nm、通道濃度設計為5x1018 cm-3時，將有助於元件展現最佳的次臨界擺幅；偏置深度對於元件次臨界特性影響不大，僅影響串連電阻；垂直通道的長度隨著閘極高度壓低而縮短。決定元件最佳參數後，便對元件之單閘極與雙閘極操作模式進行模擬比較。結果顯示雙閘極操作下能提供較好的閘極控制能力，而單閘極操作下上部閘極的控制能力又優於下部閘極。

In this paper we will discuss the stimulation of Vertical Channel Junctionless Thin-Film Transistors by the electrical characteristics. First, we created the device structure by process simulation tool: Making a vertical junctionless channel of polysilicon by isotropic deposition with in-situ doping method. To find out the best control parameter, we adjusted the channel thickness, phosphorus concentration, offset depth, and channel length according to the subthresshold characteristic. We found that the device will perform the best subthreshold swing when its channel thickness designed at 10nm and the channel concentration at 5x1018 cm-3. However, the offset depth does not impact the subthreshold characteristic much but series resistance. We started to compare the Single Gate operation and Double Gate operation once parameter been defined. The results show that the device performs a better Gate control under Double Gate operation.