應用於三維結構電路整合之薄膜電晶體

Abstract

我們成功製造出第一部份所提出的高效能垂直通道多晶矽薄膜電晶體；利用雙閘極和無接面等技術期望製作出可媲美單晶矽元件特性的薄膜電晶體，並仔細探討其電特性。研究中我們不但發現通道層厚度對於此類元件的載子傳輸是一項極為關鍵的參數，更應用鎳矽化物技術以進一步降低串聯電阻而使汲極電流獲得提昇與改善。在變溫的的量測中則可以發現隨著溫度增加，有臨界電壓下降、次臨界擺幅倒塌、導通電流增加等現象發生；產生這些現象的原因將於此研究中被仔細探討。

We study the characteristics of vertical channel poly-Si thin-film transistors that are junctionless and double-gated. Channel film thickness is a crucial factor in carrier transport. The drain current can be improved by Ni-salicidation technology since it reduces the series resistance. The threshold voltage decreases as temperature increases. The subthreshold slope, off-state leakage current and on-state current also increase as temperature increases.