具抗製程、電壓、溫度變異之超低電壓數位操控穩壓器應用於超低功率動態調節電壓頻率系統

Abstract

隨著製程技術不斷地演進，類比式電壓調節器在設計上越來越困難，並且在製程轉移的情況下，很難快速將產品推向市場以滿足現今的需求。為此，本論文提出了一個全數位化控制的線性電壓調節器。然而，當操作環境在近/次臨界電壓時，環境變異會產生重大的影響，因此，對製程、電壓、溫度變異的偵測系統設計是關鍵並且重要的。經由模擬，本論文所提出的數位電壓調節器可以實現高達99.5％的電流效率。這項設計具有兩大優勢：快速響應時間60ns和處於穩定狀態時的低靜態電流162μA。從系統啟用到穩定在0.3V的時間約為138ns。 並切，經由採用製程、電壓、溫度感知的數位錯誤偵測器，在面臨環境變異時，可將輸出電壓錯誤率降50%。而使用智能漣漪降低法可改善輸出漣漪高達78％。調節電壓在0.51V時可達到最好的FOM 0.33 pA‧s。整個電壓調節器的總面積是388.6×35.7μm2。使用是台積電65奈米低功耗CMOS製程。電壓調節器的輸出以每30mV為一階，可從0.3V調整至0.51V，而其分辨率降並不會因為環境變異而降低。

Due to analog regulator design is hard to meet the fast time-to-market time as technology continues migration; an all-digital controlled linear regulator is proposed. However, Environment variations are severe in ultra-low voltage region. In order to enable linear regulator near-/sub-threshold operation, PVT-aware design is paramount. The proposed digital voltage regulator can achieve up to 99.5% current efficiency. This work has two major advantages: fast response time of 60ns and low quiescent current 162μA in stable state. The settling time is about 138ns. The output voltage error in 0.3V stable states error improvement of the resolution using PVT-aware DED is around 50%. The improvement of output ripple using smart ripple reduction method can up to 78%. The best FOM at the regulated voltage (VREG) equals to 0.51V is 0.33 pA‧s. The total area of whole regulator is about 388.6×35.7μm2 using TSMC 65-nm low-power bulk CMOS technology, which can produce VREG from 0.3V ~ 0.51V in steps of 30mV without resolution degrading under PVT variations.