應用於RS 碼及BCH 碼之關鍵方程式求解器設計及實作

Abstract

在現今的數位通訊系統中，為了提供品質更好的使用者體驗，所需之資料傳 輸率大幅上升；對於資料吞吐量的要求也隨之提高。為了達到此需求，系統上常 採用多通道之設計。由於錯誤更正碼編解碼器乃是傳輸路徑上提升資料傳輸可靠 度之關鍵一環，為了支援多通道設計需降低此單元之時間延遲，以便在相同時間 內處理多個傳輸通道之資料。然而，一般針對此需求設計之錯誤更正碼解碼器之 硬體複雜度往往會大幅增加。因此，我們的訴求希望能在滿足應用條件之下，設 計出低複雜度之錯誤更正碼解碼器。在此篇論文中，我們提出了兩種方法分別針 對於BCH 碼以及RS 碼中的低延遲關鍵方程式求解器。BCH 碼和RS 碼被廣泛 應用在於光通訊、第二代數位影像廣播衛星以及固態硬碟等應用中。而關鍵方程 式求解器則在BCH 及RS 的解碼器中，佔據很大部分面積。因此我們將針對兩 種特定的應用，降低關鍵方程式求解器的複雜度並維持其規律的結構。 對於下一世代的光通訊系統中，RS(255,239)碼是被採納做為其錯誤更正碼之 一。為了達到100Gb/s 的系統要求，每組RS 解碼器須達到6.25Gb/s 的吞吐量。 我們所提出的關鍵方程式求解器使用一個反向器取代了交叉相乘的運算，成功地 下降了硬體複雜度。此演算法在高更錯能力的設計中，會有更好的效果。 而為了滿足下一代的固態硬碟需求，我們實現了有124 位元更錯能力的BCH (18244, 16384)碼。我們設計的低延遲關鍵方程式求解器減少了42%的邏輯數量 並且與其他當今的錯誤更正碼解碼器文獻相比亦極具競爭力。我們設計的晶片是 採用UMC 90nm 製程，並可同時支援八通道的徵兆值產生器以及秦式搜尋器， 且可運作在198MHz 頻率下，達到12.6Gb/s 的吞吐量。

Among contemporary digital communication systems, the transmission rate becomes higher and the systems require low-latency design to reduce the access time. Since the cost of the error correction code (ECC), which is the inevitable part of the transmission systems, is incredibly increasing under high throughput applications, it is a big challenge to design ECC in an area-efficient architecture. In this thesis, we presented two approaches of low-latency key equation solver (KES) for BCH and RS codes, which are widely used in optical communications, digital video broadcasting-satellite-second generation (DVB-S2), and solid state drives (SSD) applications. Note that the KES of the RS or BCH codes dominate the whole decoder and therefore, we only focus on how to reduce the hardware complexity while maintaining the regular structure and high speed operation of KES in two specific systems. For the next generation of optical communication systems, the RS(255,239) is an adopted specification to reach the throughput of 6.25Gb/s in order to support 100Gb/s system requirement. By replacing the multipliers with an inverse operation, the proposed KES architecture can eliminate the cross-multiplication computation to successfully reduce the hardware complexity. This synthetic division on Euclidean (SDE) algorithm performs well especially when the high error correctability is needed. To meet the requirement of the next generation of SSD, the BCH (18244, 16384)code with error correct capability 124bits is implemented. Our design applying the low-latency KES, which can reduce at least 42% gate count compared to traditional low-latency KES, is highly competitive with other state-of-the-art decoders. After fabricated in UMC 90nm, the proposed KES chip can simultaneously support 8-channel syndrome generators and Chien search logics to achieve 12.6Gb/s throughput under 198MHz operation frequency.