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dc.contributor.author洪政豪en_US
dc.contributor.authorHong, Zheng-Haoen_US
dc.contributor.author陳巍仁en_US
dc.contributor.authorChen, Wei-Zenen_US
dc.date.accessioned2014-12-12T02:38:08Z-
dc.date.available2014-12-12T02:38:08Z-
dc.date.issued2013en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079911665en_US
dc.identifier.urihttp://hdl.handle.net/11536/73483-
dc.description.abstract本論文提出一個操作在25Gbps接收器,由連續時間線性等化器與內建2-tap決策回授等化器的時脈資料回復電路組成。操作在19Gbps到25Gbps的範圍中,混合式的半速率時脈資料回復電路能幫助消除符際干擾與資料抖動。並提出一個不需使用電感並提供取樣時脈相位的四相位弛張震盪器。此晶片使用台積電四十奈米互補式金氧半導體製程,全部接收器消耗84.5毫瓦,操作在1.2伏特電壓,晶片核心電路面積為0.09平方毫米。zh_TW
dc.description.abstractThis paper describes a 25-Gb/s receiver comprising of a continuous time linear equalizer followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit. The hybrid half-rate CDR facilitates ISI and jitter suppression over 19 Gbps-25Gbps operation. A quadrature relaxation oscillator provides the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver consumes 84.5 mW from 1.2 V supply with a core area of 0.09 mm2.en_US
dc.language.isozh_TWen_US
dc.subject時脈資料回復電路zh_TW
dc.subject決策回授等化器zh_TW
dc.subjectCDRen_US
dc.subjectDFEen_US
dc.title25Gbps等化器與時脈資料回復電路zh_TW
dc.title25Gbps Equalizer and Clock and Data Recovery Circuiten_US
dc.typeThesisen_US
dc.contributor.department電子工程學系 電子研究所zh_TW
Appears in Collections:Thesis