一個低電壓基於時間三角積分類比至數位轉換器

Abstract

本篇論文提出一個低電壓基於時間三角積分類比至數位轉換器，訊號頻寬為2MHz，操作在時脈頻率為250MHz，供應電源電壓從0.3V~0.44V，並擁有等校位元解析度6.6 ~ 8.4 bits。本系統使用連續時間二階三角積分調變，超取樣率為62。為了使低電壓下可以得到高頻寬需求，本電路架構使用了許多電位提昇方法，來克服先天供應電源電壓的不足。此晶片使用台積電九零奈米互補式金氧半導體製程，全部數位至類比轉換器共消耗0.415毫瓦至1.215毫瓦，晶片核心電路面積約為0.08平方毫米。

This thesis presents an ultra-low voltage time-based delta-sigma analog-to-digital converter. The bandwidth, sampling clock, supply voltage and ENOB of this converter are 2MHz, 250MHz, 0.3V~0.44V and 6.6 ~ 8.4 bits respectively. The ADC uses a 2nd order continuous time delta-sigma modulator, of which oversampling ratio is 62. In order to operate the system in requirement of a high bandwidth, several circuit technique are designed for increasing the voltage level to conquer the low supply voltage. The chip is fabricated in a 90 nm general purpose CMOS technology. The whole ADC consumes 0.415 mW to 1.215 mW from 0.3 to 0.44 voltage supply with a core area of 0.08 mm2.