考慮嵌入不同大小之緩衝器的時鐘樹合成

Abstract

為了要成功設計高效能的積體電路晶片，時鐘樹合成扮演了非常重要的角色。時鐘樹的時脈偏移會直接影響晶片的效能。在這篇論文當中，我們提出了一個新的繞線電阻模型，而這個繞線電阻模型是根據商業用軟體（Encounter）抽取出實際的繞線電組所建立的。導通孔電阻是繞線電阻的一部分，而且不可輕易忽略。我們發現導通孔電阻和該條繞線的外接點的數量有關聯。我們採用傳統的訊號轉換模型，來決定每種緩衝器可以接受的最大電容負載。我們根據方才決定的最大電容負載，來選擇放入緩衝器的位置以及大小。在完成建立時鐘樹之後，我們會將我們的結果和Encounter 建出來的時鐘樹作比較。雖然我們的結果稍微比Encounter 的結果差，但是我們的執行時間卻比Encounter快上許多。

Clock tree synthesis plays a vital role to achieve a successful high performance chip design. Clock skew influences the chip performance directly. In this work, we propose a new wire resistance model based on the actual wire resistance extracted by a commercial tool, Encounter. Via resistance is a part of wire resistance and cannot be negligible. We find that via resistance of a net is related to its fan-out number. We adopt a traditional slew model to decide the maximum output capacitances of buffers that are used as the criteria of buffer insertion/sizing. After clock tree construction, we compare our result with the clock tree generated by Encounter. Although our result is worse than Encounter, our run time is much faster than Encounter.