應用於癲癇偵測之低能耗快速獨立成分分析處理器之設計與實作

Abstract

獨立成分分析能夠分離多通道腦波中的雜訊和癲癇訊號以提升癲癇偵測之效能。快速獨立成分分析是一種高效率計算獨立成分分析的演算法。為了降低能量消耗，前處理採用特徵值分解以降低獨立成份的迭代次數。特徵值分解利用高平行度架構快速運算。以近似的Jacobi演算法實現的特徵值分解電路和過去的文獻相比降低77.2%。儲存資料的記憶體部分因為記憶體的選擇和適當的wordlength省下95.6%功耗和51.7%面積。透過架構最佳化過程，我們找出晶片面積最小的架構。在latency constraint為0.1s的情況下，和沒有經過最佳化的架構相比面積省下86.5%。core area是0.40mm^2，以90nm CMOS製程實現。快速獨立成分分析處理器操作於0.32V時功耗為81.6W，未來也將整合於癲癇控制系統晶片。一段八通道256個採樣的腦波需要84.2ms的運算時間。和文獻相比，我們只花0.5%功耗，26.7%面積就能加速3.4倍。晶片的功能已經由病人腦波驗證。

To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. To reduce the energy dissipation, eigenvalue decomposition (EVD) is utilized in the pre-processing stage to reduce the convergence time of iterative calculation of ICA components. EVD is computed efficiently through an array structure of processing elements running in parallel. Area-efficient EVD architecture is realized by leveraging the approximate Jacobi algorithm, leading to a 77.2% area reduction. By choosing proper memory element and reduced wordlength, the power and area of storage memory are reduced by 95.6% and 51.7%, respectively. The chip area is minimized through architectural transformations. Given the latency of 0.1s, an 86.5% area reduction is achieved compared to the direct-mapped architecture. Fabricated in 90nm CMOS, the core area of the chip is 0.40mm^2. The FastICA processor, part of an integrated epileptic control SoC, dissipates 81.6W at 0.32V. The computation delay of a frame of 256 samples for 8 channels is 84.2ms. Compared to prior work, 0.5% power dissipation, 26.7% silicon area, and 3.4 computation speedup are achieved. The performance of the chip was verified by human dataset.