高能源效率之訊號分離系統設計與實現

Abstract

本論文中探索兩個高能源效率之訊號分離系統。我們認為可透過減少演算法的運算複雜度來達到高能源效率之訊號處理電路設計。我們對兩個訊號分離系統各自提出減少運算複雜度的方法，並且實現相對應的硬體設計以驗證所提出之方法能達到高能源效率。 在非盲訊號分離系統：平坦衰退通道下之空間多工多輸入多輸出偵測系統中，本論文提出一個高能源效率且多模式多輸入多輸出訊號偵測器，其使用本論文所提出的適應性列舉長度方法，此偵測演算法可依據通道情況調整列舉長度來減少運算複雜度。此多輸入多輸出訊號偵測器支援2×2/4×2/4×4之多輸入多輸出系統與QPSK/16-QAM/64-QAM調變，並擁有低複雜度與令人滿意的偵測效果。在硬體架構方面，本論文提出基於區域切割的多符元選擇器架構與適應性列舉長度選擇單元、可擴展之樹狀搜尋與局部歐幾里德距離單元、可擴展之平行管線化排序網路架構以減少多輸入多輸出訊號偵測器功率消耗並增加其吞吐量。此多輸入多輸出訊號偵測器使用台積電0.18μm製程製造，在電壓為1.8伏特的情況下，最高操作頻率為107 MHz。在4×4 64-QAM之多輸入多輸出系統下，吞吐量為1284 Mbps，功率消耗為282.6 mW，其能源效率為220.1 pJ/bit。與沒有使用適應性列舉長度方法的設計比較，此多輸入多輸出訊號偵測器在僅損失0.1 dB的情況下能減少45.49%的功率消耗。 在盲訊號分離系統：使用獨立成分分析之腦波訊號分離系統中，本論文提出一個高能源效率的快速獨立成分分析器，其使用本論文所提出的提早終止機制，並可用來分解八通道的腦電波訊號。其主要貢獻包含1) 提出提早終止機制與其相對應的硬體架構; 2) 提出高成本效率的前處理單元架構，其包括基於單一CORDIC的特徵值分解器與使用硬體重覆利用方式的one-unit架構; 3) 使用4套平行one-unit架構以達到低運算時間。此快速獨立成分分析器使用聯電90 nm製程設計，其晶片面積為1.221×1.218 mm2，經過晶片佈局後的模擬，在電壓為1伏特的情況下，最高操作頻率為100 MHz。在分解八通道腦電波的情況下，功率消耗為16.35 mW，最長的運算時間為0.29秒。與沒有使用提早終止機制的設計比較，此快速獨立成分分析器能減少47.63%的能源消耗。

In this dissertation, two energy-efficient signal separation systems are explored and implemented. Energy-efficient VLSI signal processing design can be achieved by reducing computational complexity in the algorithm level. Many computational complexity reduction schemes are proposed for two signal separation systems, and the corresponding VLSI architectures are implemented to show the energy efficiency. In nonblind signal separation system, considering spatial multiplexing MIMO detection system under flat fading channel, an energy-efficient multimode multiple-input multiple-output (MIMO) detector using a modified adaptive list length scheme is presented. The list length is selected according to the channel condition to reduce computational complexity. The proposed MIMO detector supports 2×2/4×2/4×4 antenna numbers with QPSK/16-QAM/64-QAM inputs and possesses low complexity with satisfactory bit error rate (BER) performance. In terms of architecture, we propose a region-partition-based multiple-symbol selection (RPMSS) architecture with a modified adaptive list length selection (MALLS) unit to lower the power, a scalable tree search with PED calculation (STSPC) unit and a scalable parallel-pipeline sorting network (SPPSN) architecture to enhance the throughput of the MIMO detector. The resulting MIMO detector in TSMC 0.18 μm 1P6M CMOS process possesses maximum throughput of 1,284 Mbps and core area of 2.56 mm2 with 210 K gates. The power dissipation of the 4×4 MIMO system with 64-QAM inputs is 282.6 mW@107 MHz at 1.8V, and the resulting energy efficiency is 220.1 pJ/bit. Moreover, compared with the design without the modified adaptive list length scheme, the proposed MIMO detector achieves power reduction by 45.49% with loss of 0.1 dB. In blind signal separation system, considering electroencephalogram (EEG) signal separation system using independent component analysis (ICA), an energy-efficient fast independent component analysis (FastICA) implementation with an early termination scheme for eight-channel EEG signal separation is presented. The main contributions are as follows. 1) Energy-efficient FastICA architecture using the proposed early termination scheme; 2) cost-effective FastICA using the proposed preprocessing unit architecture with one CORDIC-based eigenvalue decomposition (EVD) processor and the proposed one-unit architecture with the hardware reuse scheme; 3) low-computation-time FastICA using the four parallel one-units architecture. The resulting power dissipation of the FastICA implementation for eight-channel EEG signal separation is 16.35mW@100MHz at 1.0V. Compared with the design without early termination, the proposed FastICA architecture implemented in UMC 90nm 1P9M CMOS process with a core area of 1.221×1.218 mm2 can achieve average energy reduction by 47.63%. From the post-layout simulation results, the maximum computation time is 0.29 second.