應用於四通道EEG訊號分離之低功耗FastICA設計與實現

Abstract

在本論文中，我們針對FastICA演算法設計一個應用於四通道EEG訊號分離低功耗的架構。為了達到低功耗，主要提出三個方法1) 混合型定點數運算單元與浮點數運算單元之系統；2) 在資料前處理使用單一坐標旋轉數位計算機實現特徵值分解處理器；3) 雙曲正切函數使用分段線性逼近應用於定點迭代法。 低功耗的FastICA架構使用TSMC 0.18um CMOS 製程，其晶片面積為2.25 mm2。在操作頻率為50 MHz與操作電壓為1.8伏特的情況下，最大功率消耗為7.662 mW。

This thesis presents a low-power VLSI architecture for fast independent component analysis (FastICA) with the application to four-channel EEG signal separation. The proposed low-power schemes are as follows. 1) hybrid of fixed-point and floating-point number system; 2) CORDIC reuse scheme for eigenvalue decomposition (EVD) in the preprocessing part; 3) piecewise linear approximation for hyperbolic tangent in fixed-point iteration algorithm. From the experimental results, the satisfactory correlation coefficient can be achieved. The low-power FastICA implemented in TSMC 0.18um CMOS technology process consumes 7.662 mW at 50 MHz at 1.8 voltage with the size of 2.25 mm2.