應用於八通道EEG訊號分離之高能源效益FastICA設計與實現

Abstract

在本論文中，我們針對FastICA演算法設計一個應用於八通道EEG訊號分離高能源效益且具有高維度前處理的FastICA處理器。我們主要貢獻描述如下。1) 使用提早中止學習的技巧來達成高能源效益FastICA；2) 在資料前處理使用單一坐標旋轉數位計算機來實現高維度且低面積的特徵值分解處理器；3)使用四套one-unit同時運算來達成低運算時間；4)使用高精準度的分段線性逼近雙曲正切函數用於one-unit的運算；5) 使用硬體重複使用技巧來實現低面積的one-unit 架構。 在操作頻率為100 MHz與操作電壓為1.0伏特的情況下，最大功率消耗為16.35mW。提出的FastICA架構使用UMC 90nm CMOS 製程，其面積為1.221x1.218mm2，且與沒有使用提早中止學習的技巧做比較，其功率可以省41.38%。從硬體模擬結果來看，混合訊號最差之絕對值相關係數可達到0.98且腦波訊號最差可達到0.83。

This thesis presents an energy-efficient fast independent component analysis (FastICA) processor with high-dimensional preprocessing unit for eight-channel electroencephalogram (EEG) signal separation. The main contributions are as follows. 1) Energy-efficient FastICA using early determination scheme, 2) high-dimensional and low-area eigenvalue decomposition (EVD) using CORDIC reuse scheme for the preprocessing unit; 3) low computation time using four parallel one-unit architecture; 4) high-accuracy piecewise linear approximation for the hyperbolic tangent in one-unit operation; 5) low-area one-unit architecture using hardware reuse scheme. The resulting power dissipation of the FastICA computations for eight-channel EEG signal separation is 16.35mW@100MHz at 1.0V. Compared with the design without early determination, the proposed FastICA processor implemented in UMC 90nm 1P9M CMOS process with a core area of 1.221x1.218 mm2 can achieve energy reduction by 41.38%. From the post-layout simulation results, the absolute correlation coefficients for mixed signals and EEG signals are at least 0.98 and 0.83, respectively.