積體電路金屬互連線間介電層之電場分析

Abstract

發展下一世代積體電路，金屬互連線間距離縮短，造成互連線間介電質之電場強度上升。這可能導致金屬互連線間介電層崩潰。進而導致電路功能故障。 為了瞭解上述現象，本論文利用Mentor Graphics之Calibre設計工具撰寫程式篩選出在IC電路操作中可能發生金屬互連線間介電層崩潰之金屬線樣式。Cadence之Virtuoso Layout Editor軟體用來顯示並標記所篩選之金屬線。Synopsys之Raphael模擬軟體用來分析此金屬線電場。 本研究在0.18µm製程之積體電路中，歸納出在Metal-1層之角對角金屬線樣式最有可能造成金屬互連線間介電層之崩潰現象。此結果是因為它的最小設計規則較嚴苛，且出現在Metal-1層的次數較為頻繁。 本研究也顯示以0.18-µm製程製造之積體電路，在供應電壓為1伏特情況下，金屬互連線間介電質之平均電場強度約為0.3~0.4MV/cm。當供應電壓改為3伏特時，此電場強度上升至約為0.9~1.2 MV/cm。

Scaling the next-generation Integrated Circuits (ICs) has shorten the distance between interconnected lines which increases electrical fields between them. This may cause breakdown in dielectrics between interconnect line during IC operation, resulting in malfunction of the ICs. To understand such phenomenon, Mentor Graphics’ Calibre tool was utilized in this thesis study where specific layout patterns with higher possibility of interconnect dielectric breakdown during circuit operation were filtered and selected with some DRC commands. There selected patterns were marked and viewed using Cadence’s Virtuoso Layout Editor tool. The analysis of the electric fields in this patterns were performed by Synopsys’s Raphael tool. The study concludes corner-to-corner Metal-line patterns at Metal-1 layer are most likely to cause interconnect dielectric breakdown due to the frequency of this occurrence and the strictest minimum design rule of Metal-1. The study also reveals that the average electric field in interconnect dielectric is around 0.3 to 0.4 MV/cm with the IC supply voltage of 1V by a 0.18-µm IC layout. As IC supply voltage changed to 3V, this electric field was up to around 0.9 to 1.2 MV/cm.