使用最小線間距之低功率高速晶片內部匯流排電路設計

Abstract

本論文提出一個使用最小線間距之低功率晶片內匯流排系統，工作電壓操作在臨界電壓上，大幅降低功率消耗。為了要節省面積的支出因此晶片內匯流排將採取最小線距，此舉讓線間耦合電容大幅上升，耦合效應也隨著耦合電容得增加造成更嚴重的信號抖動。為了要避免耦合效應之影響，常見的方式為加入屏蔽線接地包圍在信號線間，而此作法將大幅增加負載讓速度下降並消耗更多功率，因此我們採取部分屏蔽式匯流排架構，如同完全屏蔽讓耦合效應得到抑制又有較小的負載，較小的負載能減輕ISI效應，讓ISI效應與耦合雜訊得以取得最佳的平衡點。藉此讓匯流排得到足夠的保護以抑制信號抖動，相對較小的負載又能減少功率的消耗並讓速度提升。

本論文以TSMC MSG90製程製作，操作電壓為1V，TT corner下資料速率可達2Gbps，功率消耗為5.38mW，晶片布局面積為1mm2 (1mm×1mm)。

This thesis proposes a low power on-chip bus with minimum spacing. The supply voltage is near the threshold voltage of MOSFET to reduce the power consumption. To save the chip area we use minimum spacing, but this arrangement will increase the coupling capacitance between wires. With the increasing of coupling capacitance, jitter which due to coupling effect becomes more and more serious. This thesis proposes a partial shielding design. It protects wire from couple effect as fully shielded bus but with less loading. The less loading from ground shielding alleviates the inter symbol interference. The compromise between coupling noise and ISI effect can be optimized. It lets the bus be protected appropriately to be free from coupling jitter. At the same time, lets the power consumption decrease and data-rate increase with loading decrease. The chip is implemented in TSMC MSG90nm process, and the supply voltage is 1V. At TT corner, the data rate is 2Gbps. The total power is 5.38mW, the chip area is 1mm2 (1mm×1mm).