藉由晶圓接合從藍寶石基板剝離氮化鎵技術

Abstract

高亮度發光二極體 (light emission diodes, LED) 近年來蓬勃發展並且廣泛使用在路燈、汽車頭燈、螢幕背光板以及投影機等常見日常生活用品上。發光二極體主要受限於熱和發光效率的不良影響而導致效率不彰，而主要生長氮化鎵發光二極體的基板為藍寶石基板，圖型化藍寶石基板（patterned sapphire substrate, PSS）近年來常被用來改善磊晶品質以增加內部量子效率以及光取出效率。然而藍寶石基板為不好的散熱和導電的基材，進而影響到後續元件的品質和效率，目前業界最常使用剝離藍寶石基板的方法為雷射剝離（laser lift-off, LLO），然而雷射剝離設備相當昂貴且會造成磊晶層損傷，進而增加元件內部缺陷與造成漏電流產生。為了改善剝離成本與技術，我們提出一個新的方法，從藍寶石基板上剝離氮化鎵磊晶層。 本實驗使用側面環繞二氧化矽層之PSS，在成長氮化鎵磊晶層後，有效的在基板與磊晶層介面間流下孔洞，使得接觸面積大為下降，使用晶圓接合技術將其接合至良好導熱導電的銅基板上，利用氮化鎵磊晶層與藍寶石基板34%的熱膨脹係數差異，進行高低溫差循環(thermal cycle)以及化學蝕刻補助實驗，使熱應力集中於氮化鎵與PSS的接觸面，造成氮化鎵剝離並附著於銅基板上。 本實驗分為兩大部分。第一部分又包含前後部分，前部分以thermal cycle溫差不同分為：350℃~室溫(Lift-off at room temperature, LO-RT)、350℃~0℃(Lift-off at 0℃, LO-0C)，實驗後部分以化學蝕刻次序不同分為：thermal cycle居間搭配化學蝕刻 (KOH lift-off mediate, KLO-M)、優先化學蝕刻後thermal cycle (KOH lift-off advanced, KLO-A)。實驗第二部分，在PSS上用氮化鋁緩衝層(AlN buffer layer)成長氮化鎵LED結構，在晶圓接合至銅基板後，利用化學蝕刻對氮化鋁與氮化鎵的選擇比，造成氮化鋁底部側向蝕刻(under-cut)從PSS上剝離淡化鎵，將此部分實驗名為chip lift-off。 實驗結果發現LO-RT與LO-0C氮化鎵完整剝離面積均不及1chip size (225 x 525μm2)，但剝離後的氮化鎵表面有PSS圖案轉印於其上。KLO-M剝離結果接近1 chip size，並發現剝離後氮化鎵表面與LO-RT、LO-0C明顯不同，找出其蝕刻順序與磊晶品質和晶體方向有關，且將蝕刻後的特定晶面計算出為{10-1-1}晶面族。在KLO-A實驗結果顯示成功剝離完整氮化鎵面積達數10 chip size以上，證明使用化學蝕刻能讓磊晶層與PSS基板間接觸面積更有效下降，使得在熱應力集中後能產生更大的剝離面積。X-ray rocking curve顯示無論是GaN-(001)和GaN(002)的半高寬值，在KLO-M、KLO-A剝離之後均升高，說明剝離過程造成氮化鎵磊層的損害。Chip lift-off實驗結果顯示，由於PSS與磊晶層之間並沒有留下孔洞以及AlN緩衝層太薄，使得化學蝕刻液無法有效進行物質交換造成under-cut，因此只有元件方格(chip-mesa)周邊的氮化鎵剝離至銅基板上。

GaN-based light-emitting diodes (LEDs) have been utilized in traffic lights, as backlights on liquid crystal displays, and in white LEDs. In order to improve the efficiency of LEDs, the idea of patterned sapphire substrates (PSS) has been brought out. Owing to low thermal and electrical property of sapphire, we have to replace for a better property substrate. After wafer bonding the epitaxial layers of onto a conductive substituting substrate, sapphire substrate needs to be lifted off such that the LEDs output power can be enhanced. Nowadays, the most commonly used approach for removing sapphire substrate is the laser liftoff technique (LLO). However, in this high-cost technique, with high-power ultraviolet (UV) laser illumination, the LEDs wafer can be cracked and damaged. Therefore, we bring out the idea of bonding lift-off. We introduce the SiO2 lateral around PSS method, by this method periodic voids remain between the interface of GaN and PSS. Then using wafer bonding technique to bond it onto Cu substrate. Owing to the 34% difference of GaN and sapphire substrate’s thermal expansion coefficient (CTE), during thermal cycle and chemical solution etching process, thermal stress concentrate at the reduced contact area to lift-off GaN from PSS. The experiment divided into two big parts. Then first big part divided into front part and back part. The front part including LO-RT ( lift-off from 350℃ to room temperature) and LO-0C (lift-off from 350℃ to 0℃).The back part including KLO-M (KOH lift-off mediate during thermal cycle of 150℃ to 0℃) and KLO-A (KOH lift-off advanced during thermal cycle of 150℃ to 0℃). The second big part: Using AlN buffer layer to grow GaN LEDs device on PSS, then bonding to Cu substrate. By chemical solution selective etching of AlN and GaN to under-cut etching AlN buffer layer and then lift-off GaN from PSS. We his named this process Chip lift-of. The results of LO-RT and LO-0C indicate that the lift-off GaN area is much less than 1 chip size (225 x 525μm2). But we find out that dot patterns on surface of lift-off GaN is transferred by PSS dot patterns. KLO-M result indicate lift-off GaN area is near to 1 chip size. Besides, we discovered that the surface morphology of KLO-M lift-off GaN is much different from LO-RT and LO-0C lift-off GaN. Then we figure out that the etching priority is related to crystal quality and crystal direction. And calculate out the specific etching facet is {10-1-1}. KLO-M result indicate that lift-off GaN area is much more than 1 chip size. It’s reveal that chemical etching can reduce more contact area of GaN/PSS effectively. X-ray rocking curve result indicate that both of GaN-(002) and GaN(102)’s Full width at half maximum (FWHM) is increased largely after GaN lift-off from KLO-M and KLO-A. It’s means that the crystal quality of GaN is damaged during lift-off process. Chip lift-off result indicate only little part around chip mesa of GaN is lift-off. It’s because the AlN buffer layer is too thin and no voids between interface of GaN/PSS. Thus chemical etching solution can’t do mass transport effectively to under-cut AlN buffer layer.