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dc.contributor.author張繼文en_US
dc.contributor.authorChi-Wen Changen_US
dc.contributor.author陳昌居en_US
dc.contributor.authorChang-Jiu Chenen_US
dc.date.accessioned2014-12-12T02:39:01Z-
dc.date.available2014-12-12T02:39:01Z-
dc.date.issued2004en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009217579en_US
dc.identifier.urihttp://hdl.handle.net/11536/73824-
dc.description.abstract一般人所熟悉的轉換搜尋緩衝器是用來將虛擬記憶體轉換成實體記憶體的一種機制,在整個電腦系統運作中扮演極重要的角色。如果有任何的失誤發生時,都會造成處理器的效能嚴重的下降。為了減低任何失誤的可能性發生,有不少的研究方法和理論被提出。有些理論是利用改進轉換搜尋緩衝器的關聯性或增加其容量大小來降低其因衝突產生的失誤和容量不足而導致的失誤,有些研究者則提出使用超級分頁的概念來涵蓋更多的記憶體空間。這些眾多的方法當中,特別是超級分頁對於大部分的應用程式能夠有效率的降低失誤的可能性。可惜的是對於行程切換導致轉換搜尋緩衝器效能降低方面的研究卻是少之又少。為了支援近代的作業系統當中都有多重程式操作的特色,作業系統必須要有行程環境切換機制以方便將正在處理的行程切換到下一個行程,此時須清除目前轉換搜尋緩衝器所暫存的位址轉換資訊。而清除轉換搜尋緩衝器資訊的這樣一個行為,將會造成處理器效能嚴重的下降,特別是對於近代高效能的處理器。這篇論文提出了一種新穎且容易實作的轉換搜尋緩衝器架構來降低行程環境切換機制所帶來的損失同時我們更整合多重分頁的機制來降低失誤的機會。我們修改SimpleScalar 3.0d 模擬器及使用SPEC2000 作為我們的模擬平台環境,並比較其它轉換搜尋緩衝器的架構,模擬結果顯示出所提出的轉換搜尋緩衝器架構在傳統的4KB 分頁大小底下可以比傳統轉換搜尋緩衝器的失誤率小上1.3 倍,在此可見所提出之架構非常適合用於多重程式環境底下。zh_TW
dc.description.abstractIt is widely known that the Translation Look-aside Buffer (TLB) plays an important role in the address translation mechanism from virtual addresses to physical addresses. If any miss occur, the performance of the processor will seriously degrade. There are many methods for improving TLB performance, such as increasing the associativity, the number of entries, or page sizes, and using superpages to cover more memory spaces. These methodologies, especially superpage, can effectively reduce lots of misses for most applications. However, very few designs really focused on the context switching issue. In order to support the multiprogramming characteristics in all modern OS, the context switching mechanism is needed and it will cause all TLB entries be flushed and will impact on the performance very seriously, especially on today’s high performance processors. This thesis presents a novel and easy implemented TLB architecture to reduce the misses in context switching with complete-subblock mechanism. All simulations were done with modified SimpleScalar 3.0d tool suite and SPEC2000 benchmarks. The thesis also compares several designs, including the conventional TLB, the complete-subblock TLB, and the promotion TLB. The simulations show that the new design can achieve about 1.3 times of relative improvement of miss rate in average with 4KB page size and reveal that our methodology can be very useful for multiprogramming environment.en_US
dc.language.isoen_USen_US
dc.subject轉換搜尋緩衝器zh_TW
dc.subject多元程式作業系統zh_TW
dc.subject環境切換zh_TW
dc.subject中央處理器模擬程式zh_TW
dc.subject完全子區塊之轉換搜尋緩衝器zh_TW
dc.subject暫存器zh_TW
dc.subjectTLBen_US
dc.subjectMultiprogramming OSen_US
dc.subjectContext Switchen_US
dc.subjectSimplescalaren_US
dc.subjectComplete-subblock TLBen_US
dc.subjectcacheen_US
dc.title降低行程環境切換導致效能損失之轉換搜尋緩衝器設計zh_TW
dc.titleTranslation Look-aside Buffer with Low Context Switch Penaltyen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
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