完整後設資料紀錄
DC 欄位語言
dc.contributor.author林明輝en_US
dc.contributor.authorLin, Ming-Hueien_US
dc.contributor.author張翼en_US
dc.contributor.authorChang, Yien_US
dc.date.accessioned2014-12-12T02:39:01Z-
dc.date.available2014-12-12T02:39:01Z-
dc.date.issued2013en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT070051537en_US
dc.identifier.urihttp://hdl.handle.net/11536/73827-
dc.description.abstract本研究著重於兩個關於砷化銦金氧半場效電晶體的重要議題:砷化銦複合通道 (InGaAs/InAs/InGaAs)之能隙工程與介面能態所引致的遲滯現象之研究。 關於元件能隙工程,吾人首先藉數值模擬以探究元件磊晶結構對載子侷限能力和遷移率的影響。吾人亦探討幾種用於元件製作及量測的磊晶結構。透過實驗結果之驗證,吾人發現複合通道厚度及次通道銦含量之極佳化有益於元件電流之提升與短通道效應之抑制。 關於遲滯效應,吾人探究遲滯現象之物理原因及其對偏壓變化之相依性。吾人提出一個物理機制以解釋遲滯現象中的閥值電壓偏移,此機制亦可藉實驗結果驗證。吾人藉著推導出之方程式,研究遲滯現象對不同的偏壓變化之相依性。另外,吾人亦提出一種萃取電晶體介面能態的方法。此法免如傳統方法般使用MOS電容,可評估電晶體閘極堆疊結構之介面性質。 此外,吾人推導幾個關於砷化銦量子井場效電晶體的物理模型,如閥值電壓及閘極電容,以對元件電性有綜覽性之理解。zh_TW
dc.description.abstractThis thesis focuses on two important issues in InAs quantum well MOSFETs: the bandgap engineering of the InGaAs/InAs/InGaAs composite channel as well as the hysteresis phenomena incurred by the interface states at the high-k/semiconductor interface. With respect to the device bandgap engineering, the influence of device epitaxial structures on carrier confinement and apparent mobility was firstly investigated by numerical simulations. The epitaxial structures used for the fabrication and characterization of the devices were introduced and reviewed. Through experimental verification, we found that optimized composite channel thickness and sub-channel indium (In) composition are beneficial to the drive current and the suppression of short channel effects. With respect to the hysteresis effect, we explored the physics origin and the bias dependences of hysteresis phenomena. A mechanism was proposed to explain the threshold voltage shift in hysteresis phenomena, and it was verified by experimental results. Various bias dependences were also studied and emphasized by using the derived equations. In addition, we also proposed a new method to extract the interface state density of the transistor without using MOS capacitor like conventional methods. The proposed method was able to evaluate the interface properties of the gate stack of MOS transistors. In addition, the physical models for the threshold voltage and gate capacitance of InAs quantum well MOSFETs were developed in order to have a understanding of the electrical behaviors of devices.en_US
dc.language.isozh_TWen_US
dc.subject先進金氧半場效電晶體zh_TW
dc.subject砷化銦量子井金氧半場效電晶體zh_TW
dc.subject元件能隙工程zh_TW
dc.subject遲滯效應zh_TW
dc.subject高介電常數閘極介電質/金屬閘極zh_TW
dc.subject閥值電壓不穩定性zh_TW
dc.subjectAdvanced MOSFETen_US
dc.subjectInAs Quantum Well MOSFETen_US
dc.subjectBandgap Engineeringen_US
dc.subjectHysteresis Effecten_US
dc.subjectHigh-k Gate Dielectric/Metal Gateen_US
dc.subjectThreshold Voltage Instabilityen_US
dc.title先進砷化銦量子井金氧半場效電晶體:元件能隙工程與遲滯效應zh_TW
dc.titleAdvanced InAs Quantum Well MOSFET: Device Bandgap Engineering and Hysteresis Effecten_US
dc.typeThesisen_US
dc.contributor.department材料科學與工程學系所zh_TW
顯示於類別:畢業論文


文件中的檔案:

  1. 153701.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。