標題: | 高層級設計對布思乘法器之建議 Suggestions of High Level Booth Multiplier Design |
作者: | 許秉慧 Hsu Ping-Hui 陳昌居 Chen Chang-Jiu 資訊科學與工程研究所 |
關鍵字: | multiplier;Asynchronous;hign-level;乘法器;非同步;高階層 |
公開日期: | 2004 |
摘要: | 在乘法器設計中,布思理論,一向被視為最簡單也最有效率的設計理論之一,自從布思理論問世,直到現在,仍然有各種以布思理論做為基礎的改良出現,毫無疑問的,不論是在時間的加速上,或是硬體的減少上,布思理論能有效率的改良這兩個方面的表現,但事實上布思理論仍然有著改良的空間。基本上,同樣的架構下,使用與不使用布思理論來實做的乘法器,使用布思理論的乘法器會有較短的執行時間,但也耗電量消耗上較不經濟。 也因此我們針對布思理論做了兩種不同的改良,其中之一是為了有效率減少耗電量,而之二則是為了更有效率的加速速度上的表現。 第一種改良,則是改良加碼器的部分,而使產生的部分乘積為0的機率增加,可到達6.75%的增加,將此種改良用於非同步乘法器的設計,可使得速度上得到14.8%的加速。 第二種改良,是針對乘法中所用到的部分乘積做改良,經由改良以後可以減少非必要的switch activity發生的機率,最多可到達61%的減少,而總耗電量經過測試則是可達到29%的減少。 Booth recoding is commonly used in multiplier design. Up to now, lots of new designs based on booth algorithm had been proposed. Undoubtedly, booth algorithm speeds up multipliers and saves the hardware by reducing partial products. But it is possible to make further progress. For example, when refer to the power consumption, it is suggested that booth multiplier is less power-efficient than non-booth multiplier. The major reason is booth multipliers waste lots of unnecessary transactions, which lead to glitches. So we proposed two technique to modify booth multipliers. The first design is to change the recoding method, and increase the probability of zero partial product by 6.25%. Then we can speed up the asynchronous booth multipliers based on the characteristic of asynchronous circuit. And speed up the multipliers at most 14.8%. The second technique reduces the unnecessary switch activity happened in partial product. We can reduce at most 61% unnecessary switch activity, and decrease at most 29% power dissipation. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009217607 http://hdl.handle.net/11536/74124 |
Appears in Collections: | Thesis |