在多核心CPU平臺下用以平行化FastICA演算法之 高效率TPL處理程序

Abstract

本論文中提出在基於C#程式語言所開發之高效率Task Parallel Library (TPL)使用處理程序應用於FastICA演算法。使用本論文所提出之高效率TPL使用處理程序在運行於四核心Intel Core 2 Quad Q8200 CPU上執行FastICA演算法，在使用八通道人造訊號，資料長度為921,600下，與未平行化程式之執行時間相比減少34.88%運算時間；與單純使用TPL平行化程式之執行時間相比，減少10.04%運算時間。在使用32通道人造訊號，資料長度為2,048下，與未平行化程式之執行時間相比減少44.01%運算時間；與單純使用TPL平行化程式之執行時間相比，減少0.93%運算時間。在使用十二通道EEG訊號，資料長度為276,360下，與未平行化程式之執行時間相比減少48.27%運算時間；與單純使用TPL平行化程式之執行時間相比，減少15.12%運算時間。

This thesis proposes an efficient Task Parallel Library (TPL) utilization procedure implemented in C# programming language to parallelize the FastICA algorithm on multi-core CPU. Applying the proposed procedure for the FastICA algorithm on a four-core Intel Core 2 Quad Q8200 CPU, the execution time of an 8-channel artificial signal with data length of 921,600 can be reduced 34.88% compared to the program without TPL. Compared to the parallelized program with TPL, the proposed procedure can reduce the execution time by 10.04%. The execution time of 32-channel artificial mixed signals with data length of 2,048 can be reduced by 44.01% compared to the program without TPL. Compared to the parallelized program with TPL, the proposed procedure can reduce the execution time by 0.93%. The execution time of 12-channel EEG signals with data length of 276,360 can be reduced by 48.27% compared to the program without TPL. Compared to the parallelized program with TPL, the proposed procedure can reduce the execution time by 15.12%.