标题: 应用于人工电子耳之低功率连续时间三角积分类比数位转换器
Low Power Continuous-time Sigma-Delta A/D Converters for Cochlear Prosthesis System
作者: 许瑞瑜
Hsu,Jui-Yu
洪崇智
Hung,Chung-Chih
电信工程研究所
关键字: 连续时间三角积分调变;降频率波器;低功率;Continuous-time Sigma-Delta Modulator;decimation filter;low power
公开日期: 2013
摘要: 本篇论文中,我们将以台积电180奈米制程制作设计适用于人工电子耳系统的连续时间类比数位转换器,当中包含一个三阶连续时间三角积分调变器,取样频率为1.536MHz,讯号宽24KHz,OSR为32。为进一步降低功号,使用四位元单调切换式SAR量化器取代一般的Flash量化器。紧接在三角积分调变器后加上了三级架构的降频滤波器,把样本输出频率从1.536MHz降回音频Nyquist Rate的48KHz。文中将显示这个系统的模拟结果与布局图。
第一版晶片量测结果在输入讯号19.5KHz时最大讯号杂讯比SNR=78.2dB,75 dB动态范围,供应电压1.8v下消耗功率为410uW,晶片面积为0.539mm2。第二版晶片中三角积分调变器晶片面积为0.634 mm2,在1.8v的供应电压下消耗功率约为208uW。而三级降频滤波器面积为0.63 mm2 ,消耗功率为43.8uW,由post layout simulation的结果,可得知96.4dB的讯号杂讯与失真比。
In this thesis, the design of the A/D converters for applications of the cochlear prosthesis system will be introduced, which were fabricated in TSMC 0.18-m CMOS process. The system includes a third-order continuous-time sigma-delta modulator and a three-stage decimation filter. The sampling rate is set to 1.536 MHz with 24 kHz signal bandwidth and the OSR of 32. A four-bit monotonous switching SAR quantizer is also used in the system. Both simulation results and layout will be presented.
Results of the first chip show that for a 19.5KHz input signal, the ADC achieves a dynamic range of 75dB and a peak signal-to-noise ratio of 78.2dB, and dissipates 410uW from a 1.8-V power supply with a 0.539 mm2 active area. Post-layout simulation of the second-version chip shows that it achieves a peak signal-to-noise -distortion ratio of 96.4 dB and dissipates about 208uW from 1.8V supply voltage. The active area of the Sigma-Delta modulator is 0.634 mm2. The area of the three-stage decimation filter is 0.63 mm2 with the power consumption of 43.8uW.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079913642
http://hdl.handle.net/11536/74518
显示于类别:Thesis