解析式的非線性直流增益曲線模型運用在雙級運算放大器

Abstract

對於交換電容的積分器，為了分析非線性失真，需要直流增益曲線。這樣的過程存在耗時的缺點，也就是先使用SPICE模擬出非線性直流增益曲線，再利用得出的模擬結果計算非線性失真。本論文是提出一個運用在雙級運算放大器的非線性直流增益曲線模型。主要的目的是在設計運算放大器前，先決定一些重要的設計規格與參數，去避免設計時發生失真超出容忍值而重覆再設計之問題。我們主要實現模型的方式為運用阻抗正比於直流增益的關係，並利用雙級運算放大器之架構特性得之。在這特定的架構下，輸出阻抗的曲線可以透過輸出端電壓變化產生。最後我們提出的模型用transistor-level模擬驗證。在現今供應電壓越來越低的趨勢下，我們的模型能夠更精確。在供應電壓1.8V下，我們估計的非線性直流增益模型與transistor-level模擬的最大誤差約為±2.1%，而我們設計模擬的最大誤差低於1.58%。

Integrator based on switched-capacitor analyze nonlinear distortion, we need dc-gain curve characteristic. The disadvantage is the need to simulate dc-gain curve by SPICE, and then calculate distortion from the simulation result. In this paper we proposed a nonlinear dc-gain curve model for two-stage op-amp. The purpose of this work is to determine some design specifications and parameters before designing the op-amp circuit. To avoid distortion exceed tolerance value and repeatedly design op-amp problem. The proposed model applied to op-amp output resistance because dc-gain is proportional to resistance. In particular configurations, the output resistance curve can be traced through output voltage. The model was verified by transistor-level simulation. Supply voltage continue to scale down, the model can be more accurate. We estimated the maximum error between our model and transistor-level simulation about ±2.1% at supply voltage 1.8V. We simulated the maximum error below 1.58%.