高介電係數介電層應用於氮化鎵電晶體之特性探討

Abstract

氮化鎵是目前極為受矚目的半導體材料之一，因具備寬能隙、高崩潰電場、載子飽和速度大、較佳的熱傳導性以及耐化學腐蝕性，所以常被應用於高壓元件、高功率、高頻率的電子元件中。另一方面，由於元件尺寸不斷的微縮下，對於薄膜沉積的品質要求也提升到達原子等級。因此原子層沉積技術非常適合應用於此條件下由於其具有極佳的薄膜附著力、良好的階梯覆蓋率和高厚度均勻性等優勢。 在本篇論文中，我們採用離子佈植的方式製作源極和汲極，以及使用原子層沉積的技術沉積閘極氧化層。之後我們將對原子層沉積的技術製作在不同閘極氧化層的方式進行研究，並討論各種製程方式下應用的可行性，進而做出結果分析，期許在不久的未來中可被應用在氮化鎵元件的製程上。

GaN is one of the most attractive semiconductor materials because its wide bandgap, high breakdown voltage, high saturation velocity, and good thermal and chemical stability, which can apply to high-voltage, high-power and high-frequency electronic devices. On the other hands, the quality of thin film deposition has the requirement for atomic level because of the miniaturization in the semiconductor industry. Therefore, the technique of ALD is suitable for the condition due to it has the advantage of excellent film adhesion, good step coverage, and thickness control uniformity. In this thesis, we use ion-implantation to form source and drain, the gate dielectric deposited by ALD. We research different high-k gate dielectric and consider the applicable feasibility on GaN fabrication technique. We analyze the results, and hope that the process can be used to fabricate GaN in the near future.