以薄膜工程製作次微米無接面銦錫氧化物薄膜電晶體及其特性分析

Abstract

本篇論文中，吾人首次以薄膜工程技術製作次微米級無接面之銦錫氧化物薄膜電晶體，並對其特性進行測量與分析。此無接面銦錫氧化物薄膜電晶體具有獨立之背閘極，其通道長度最低可達0.4微米。此薄膜電晶體之效能遠較先前發表文獻中其他銦錫氧化物薄膜電晶體為好，包括創紀錄的開關電流比(>1010)與次臨界擺幅(84 mV/decade)，並且有0.39 V之臨界電壓，使元件操作在增強型模式下。以傳統方式量測的場效電子遷移率異常地高達500 cm2/V-s以上。以正反閘極電壓掃描測量銦錫氧化物薄膜電晶體之汲極電流-閘極電壓時，吾人觀察到一獨特且有趣的逆時針方向之遲滯現象。吾人認為於多晶結構的通道中，其晶界處存在多處電子阱，電子在這些電子阱的充放電過程是造成遲滯現象之來源，並同時引起不合理的高場效電子遷移率。

In this thesis, sub-micron junctionless ITO-based thin-film transistors were fabricated by film profile engineering and characterized for the first time. The junctionless ITO TFTs feature a discrete bottom gate and a channel with smallest length of 0.4 μm. The fabricated ITO TFTs show record-high on/off current ratio of 1010 and low sub-threshold swing of 84 mV/decade. The threshold voltage is 0.39 V, indicating an enhancement-mode TFT. In addition, anomalously high field-effect mobility (> 450 cm2/V-s) is commonly seen from the characteristics of the fabricated devices. Moreover, a unique and interesting counterclockwise hysteresis phenomenon is observed in the IDS-VGS measurements. Charging and discharging of the electron traps located near or at the grain boundaries of the poly-crystalline ITO channel are considered as the origin of the hysteresis and the anomalously high field-effect mobility.