标题: | 薄膜轮廓工法-氧化锌薄膜电晶体之制作与特性分析 Fabrication and Characterization of Film-Profile-Engineered ZnO Thin-Film Transistors |
作者: | 陈品岑 Chen, Pin-Tseng 林鸿志 黄调元 Lin, Horng-Chih Huang, Tiao-Yuan 电子工程学系 电子研究所 |
关键字: | 薄膜电晶体;氧化锌;薄膜轮廓工法;Thin-Film Transistors;ZnO;Film-Profile-Engineered |
公开日期: | 2013 |
摘要: | 在本篇论文中,我们利用薄膜轮廓工法技术的概念成功制作出一个崭新结构的氧化锌薄膜电晶体,此结构的优势在于仅需要一道光罩即可完成电晶体制作。为了更进一步地了解此新结构,我们对于元件在不同的通道长度及不同的扇出(fan-out)型态下进行讨论。我们也探讨了不同沉积压力条件对于元件的影响,由于此特殊的结构设计,压力控制扮演了很重要的角色,我们可藉由调变不同材料间的沉积压力使达到自我对准的薄膜电晶体结构。为了降低源极/汲极的寄生电阻来达到提升元件特性的目的,我们也讨论了有关氩元素电浆处理对于元件特性的影响,源极/汲极区的氧化锌在经过处理后会进一步地形成一层高载子浓度的氧化锌薄膜。此外,我们也利用薄膜轮廓工法技术的概念成功制作出了实际通道长度为73nm的短通道薄膜电晶体。 In this thesis, we have successfully realized a new structure of ZnO TFTs fabricated using a novel film-profile engineering (FPE) concept, which has the merit of employing only one mask. In order to better understand about the new structure, we study the effects of different structural parameters such as channel length and types of fan-out layout of the devices. Effects of deposition pressure also have been studied. For the purpose of reducing parasitic source/drain (S/D) resistance to improve the electrical performance, we also study the impacts of the Ar plasma treatment on the S/D contact areas of the devices. Moreover, by combining film-profile engineering and method of photoresist trimming, a TFT with practical channel length of 73 nm and was realized. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT070150142 http://hdl.handle.net/11536/75025 |
显示于类别: | Thesis |