藉鎳捉聚改善鎳金屬誘發側向結晶之低溫複晶矽薄膜及奈米通道電晶體效能研究

Abstract

本論文主要研究鎳金屬誘發側向結晶(NILC)低溫複晶矽(LTPS)薄膜電晶體(TFTs)。其中，鎳金屬誘發複晶矽薄膜有鎳金屬殘留的問題，因此發展出有效的鎳金屬捉聚(Ni-gettering)方法來降低鎳金屬誘發複晶矽薄膜中的鎳金屬殘留，論文中所提出的鎳金屬捉聚結構為鎳金屬捉聚層/蝕刻停止層。鎳金屬捉聚層採用非晶矽薄膜及磷佈植非晶矽薄膜二種，厚度為100 nm。蝕刻停止層為化學法製備之二氧化矽(Chemical oxide, chem-SiO2)，厚度約5 nm。論文最後應用此鎳金屬捉聚法於鎳金屬誘發側向結晶複晶矽薄膜電晶體及矽奈米線通道電晶體(Si NW channel transistors)製作上，以探討鎳金屬對元件特性的影響。 首先，利用非晶矽薄膜及化學法製備之二氧化矽作為鎳金屬捉聚基版，成功將複晶矽中殘餘鎳捕捉至鎳金屬捉聚基板中。由SEM分析可發現鎳金屬捉聚後聚集在兩相鄰鎳金屬誘發側向結晶晶界(NILC/NILC boundary)的NiSi2蝕刻孔洞明顯減少。此種捉聚方式，是藉由濃度梯度的擴散使得複晶矽中殘餘鎳金屬能成功的透過蝕刻停止層捕捉至上層鎳金屬捉聚層，因此可發現上層非晶矽由於鎳金屬的擴散而成長出鎳金屬誘發側向結晶複晶矽。此方法與先前實驗室使用之非晶矽薄膜/電漿輔助化學沈積之氮化矽比較，可大大降低鎳金屬捉聚時間。其主要原因為鎳原子在氮化矽的擴散速度慢但通過化學氧化層卻速度快。 除此之外，為提高非晶矽薄膜之鎳金屬捉聚效率。進一步使用離子佈植法將磷雜質(Phosphorus dopant)佈植於非晶矽薄膜中，成功提高捉聚層之鎳金屬溶解度。由SEM分析可發現鎳金屬捉聚後聚集在兩相鄰鎳金屬誘發側向結晶晶界的NiSi2蝕刻孔洞幾乎不存在。磷離子佈植法雖可以提升鎳金屬捉聚效率，但其佈植濃度在1x1016 cm-2才有明顯效果。且由SIMS分析結果發現鎳在捉聚層的分佈與磷佈植曲線相當一致。 將鎳金屬捉聚法應用在鎳金屬誘發側向結晶複晶矽薄膜電晶體製備上，從元件特性得知，鎳金屬誘發側向結晶複晶矽薄膜電晶體在經過鎳捉聚處理後，可獲得較佳的電特性及均勻性，如降低漏電流(Leakage current)及抑制臨界電壓(Threshold voltage)負偏移等，其主要原因為鎳金屬誘發側向結晶複晶矽薄膜之鎳金屬殘留量可有效降低。 最後利用一個簡單及低成本的方法去製作矽奈米線通道電晶體。其製備之特點為利用一般製作MOSFET元件的側壁邊襯(Sidewall spacer)之概念，以底閘極薄膜電晶體結構在定義汲極和源極之同時，可自我對準形成奈米線通道。此複晶矽邊襯奈米線縱剖面近似三角形，其寬度及厚度可以控制至70 nm。此奈米線通道薄膜電晶體比一般傳統薄膜電晶體有比較好的通道控制能力。且經由鎳金屬捉聚處理後，鎳金屬誘發側向結晶複晶矽奈米線通道電晶體在電性與均勻性上獲得提升。主要原因為多晶矽邊襯奈米線通道內及其與氧化層之介面鎳金屬殘留量減少。

Low temperature polycrystalline silicon (LTPS) Ni-metal induced lateral crystallization (NILC) thin-film transistors (TFTs) have been investigated in this thesis. Ni impurities trapped inside the NILC poly-Si films is an issue. Therefore the Ni-gettering method is proposed to effectively reduce Ni residues within the NILC poly-Si films. It involves using gettering layers/etching stop layers as the Ni-gettering structure. The 100-nm-thick top α-Si and phosphorous-doped α-Si layers serve as the gettering layers, while the middle ~5-nm-thick chem-SiO2 layer is used as an etching stop layer. Moreover the proposed gettering method is utilized in the fabrication of LTPS NILC TFTs and Si nanowire (NW) channel transistors to investigate the effect of Ni-metal inside poly-Si on the device performance. First, the α-Si film is employed to getter Ni-silicides within NILC poly-Si film and Ni reduction is demonstrated by SEM. After the gettering process, fewer and smaller silicide-etching holes are found at the NILC/NILC boundaries. It is found that top α-Si films, Ni-gettering layers, transfer into NILC poly-Si verified by SEM. This means that during the gettering process, Ni atoms diffused from the NILC poly-Si film through chem-SiO2 into the Ni-gettering layer due to the concentration gradient. Compared with the previous α-Si/PECVD-SiNx study, the thermal budget is greatly reduced. It’s because of low Ni diffusivity in SiNx films resulting a long annealing time as 90 h at 550oC in N2 ambient. In order to improve the Ni-gettering efficiency, phosphorous-doped α-Si films are further used by ion implantation. After a gettering process, there are almost no silicide-etching holes observed at the NILC/NILC boundaries. These results indicate that phosphorous dopants could improve the gettering efficiency of α-Si due to the solubility enhancement of Ni impurities. But the gettering efficiency do not obviously improves until doping phosphorus ions reach a dose of 1×1016 cm-2. The concentration distribution of Ni is similar to that of phosphorous atoms since the projection range of phosphorous ions is set at the middle of the α-Si film. This result also indicates that phosphorus could trap Ni atoms. The proposed gettering method is further utilized in the fabrication of LTPS NILC TFTs. As NILC TFTs are treated with a Ni-gettering process, they reveal lower leakage current, higher on/off current ratio, higher mobility, and better uniformity. These improvements are all attributed to the reduction of Ni impurities in gettered poly-Si films. Finally, a simple method and low-cost process is used to manufacture the NW channels. The feature of process is the method of forming sidewall spacer of MOSFET. The poly-Si sidewall spacer NW channels self-alignment form in the process of defining source/drain (S/D). Both the vertical width (WNW) and the horizontal sidewall thickness (TNW) of poly-Si NWs are about 70 nm. The cross-section of fabricated poly-Si NWs is similar to triangular shape by an anisotropic etching. Compared with the traditional TFTs, the side-gated NWs TFTs have higher channel controllability. Moreover, the performance of NILC NWs TFTs is improved after a Ni-gettering process. This is because of the reduction of Ni and NiSi2 precipitates randomly trapped at poly-Si/gate oxide interfaces and poly-Si grain boundaries.