使用ISPP 量測方法研究改善NAND快閃記憶體可靠度問題

Abstract

隨著製程的演進，元件尺寸越來越小，也引發可靠度越來越差，如何去改善可靠度能力更顯得重要。本論文主要研究動機是怎麼去改善 可靠度，首先需要先了解一下影響可靠度的重要因素，隨著製程變小，NAND 快閃記憶體元件的浮動閘極相對縮小， 能儲存的電子數量變少，經可靠度測試後只要有少量的 charge gain or charge loss就會造成臨界電壓變動，錯誤發生。在 program/erase cycle後，我們發現選擇被 cycle 的區域會影響沒有被 cycle 區域，那些沒有被cycle 的區域在做 program 時，ISPP (Incremental Step Pulse Program)會有衰減現象，衰減的情形會隨著 program/erase cycle 區域的次數增加而變得嚴重。 經由分析，在 erase cycle 時因電壓耦合的影響，使得 WL driver(HV-NMOS) 的 SiN layer 陷入電子，造成臨界電壓增加，ISPP 因此下降。在使用 layout，電路及製程的變更後，ISPP 得到了及大改善，達到高可靠度要求。

With the evolution of the process, NAND memory cell is getting smaller. This raises reliability is getting worse. How to improve the reliability capacity is more important. The motivation of this thesis is to study how to improve reliability. First, we need to understand what a key factor of reliability issue. NAND flash floating gate size becomes smaller as the process shrink. The number of electrons stored in the floating gate become less than before process shirk. After reliability testing , when a small amount of charge gain or charge loss will cause a shift in the threshold voltage. Results is an error occurred. After the program / erase cycle, we found that the cycled region will affect the non-cycled region. Those non-cycled areas have a degradation of ISPP (Incremental Step Pulse Program) when programmed non-cycled areas. With the program / erase cycle count increased, ISPP degradation becomes serious. After electrical analyzing, we can kown that SiN layer of WL driver (HV-NMOS) trap a few hot carrier in erase cycle. This will cause the threshold voltage increases, ISPP decreased. To use three metods improve ISPP degradation issue, include layout, circuit and process. ISPP been greatly improved to achieve the high reliability requirements.