應用於可植入式醫療器件的65奈米互補式金氧半導體制程低功耗串接式鎖相迴路之設計

Abstract

近幾十年來，隨著CMOS半導體技術的快速發展，人們開始關注如何將半導體技術與其他的學術領域相結合，使得半導體技術有更廣泛的應用，例如將半導體與生醫科技做結合。在近幾年中，植入式生醫電子器件的研究也逐漸變得越來越熱門，同時有關生醫電子的一些設計標準也在這幾年內逐漸建立起來了。在2009年，美國聯邦通信委員會（FCC）為可植入式生醫電子制定了MedRadio (Medical Device Radiocommunications Service) 頻段。 這篇論文提出了一種可應用於植入式醫療器件的低功率整數型級聯鎖相環（ PLL）系統。該PLL系統利用兩個鎖相環來提供所需求的頻率的信號。系統中的第一個PLL將提供一個信號給醫療電子中的數位電路作為時鐘。這個數字時鐘信號具有大約100MHz的頻率以及50 ％占空比。系統中的第二個PLL需要提供一個MedRadio頻帶（ 401MHz 〜 406MHz）的信號作為醫療電子器件中無線傳輸的載波時脈率。為避免使用晶振，用於無限功率傳輸的線圈也將為PLL系統的工業，科學和醫療（ ISM）頻段13.56MHz的輸入參考信號。系統中的的兩個PLL被串聯連接。第一個PLL的輸出信號也將被用作第二個PLL的輸入參考。 由於本文提到的PLL 是為一個醫療電子器件服務，因此它的工作環境溫度以及工作電壓都相對穩定，但是晶片在製作過程中的變異量仍然會對整個晶片的性能造成影響，因而PLL中的環型壓控振盪器（VCO）加入了一個GM元件以降低制程變異產生的影響同時也無需外部調整。為了節省電力，在第二個PLL在數據傳輸並不工作時可以被關閉。 整個PLL系統以臺灣積體電路股份有限公司65納米互補式製程設計並實現。測量的結果表明，PLL系統可以提供一個108.48MHz ，50 ％占空比以及42.3ps 均方根抖動的方波信號作為數字時鐘，同時PLL系統也可以輸出一個在離中心頻率100kHz位移處有-74.27dBc/Hz相位雜訊的402.926MHz MedRadio頻帶的載波頻率。 PLL系統的整體功耗為0.195mW ，當第二個PLL被關閉時，系統的功耗將降低到0.066mW 。晶片面積為0.1088平方毫米。同時PLL系統沒有用到任何片外元件以及任何外部調整手段來保證PLL系統能夠正常工作，這個特性使得本論文提到的PLL系統非常適合集成進可植入生醫電子系統中。

In recent decades, with the fast development of the CMOS technology, people start to focus on the research on the probability of the combination of CMOS technology with other academic area such as medical. In this years, the implanted biomedical devices becomes a hot issue and many standards for medical devices have been published these years. The MedRadio (Medical Device Radiocommunications Service) Band is announced by Federal Communications Commission (FCC) in 2009 for implanted communication devices. In this thesis, a low power cascaded Phase-Locked-Loops (PLL) system for implantable medical devices is proposed. The PLL system is composed of two Phase Locked loops to achieve the required targets. The first PLL in the system will provide a digital clock signal for the implantable medical devices. The digital clock signal has an around 100MHz frequency and 50% duty cycle. The second PLL in the system will provide a MedRadio Band (401MHz~406MHz) signal as the carrier frequency of the radio frequency transmitter for implantable medical device. To avoiding using crystal oscillator, the wireless power transmitter coil will also provide the Industrial, Scientific and Medical (ISM) band 13.56MHz input reference for the PLL system. The two PLLs are connected in series and the PLL1’s output signal will also be used as the input reference of the PLL2. Since the PLL serves for a medical device, the operation temperature and power supply are relatively stable but the process variation of the device may influence the chip performance greatly. To reduce this impact without external tuning option, A gm unit is added into the ring-based voltage controlled oscillator (VCO) in the PLL. To save power, the second PLL can be turned off when data transmitting is not needed. The PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measurement results have shown that the PLL system can provide a 108.48MHz 50% duty-cycle square signal as digital clock with 42.3ps RMS jitter and a 402.926MHz MedRadio band carrier frequency with -74.27dBc/Hz phase noise at 100kHz frequency offset. The power consumption of PLL system is 0.195mW and when PLL2 is turned off the power consumption will reduce to 0.066mW. The chip area is 0.1088mm2. No off-chip components and external tuning option is needed to guarantee the PLL system being able to work which is suitable for the integration with the implantable medical devices.