三軸加速度計整合分頻多工讀出電路設計

Abstract

本論文提出一加速度感測系統單晶片，採用分頻多工之前端讀出電路整合三軸加速度計之設計。此感測系統全程於0.18m CMOS MEMS 製程下完成製作。該三軸加速度計設計上，提出一梯型電極設計來取代一般Z軸感測電容採用上下極板的架構並提出一複數軸向感測之電極設計來降低三軸加速度面積至0.453mm^2，相較於相同製程下之文獻減少約35%面積。 整合之多工讀出電路，其三軸輸出雜訊為9.84 V/Hz-1/2, 8.36 V/Hz-1/2 以及 7.44 V/Hz-1/2。電路功耗經電路模擬軟體Cadence所得之值為0.5583mW。經由MEMS模擬軟體Coventor，建立等效模組轉換至Cadence電路模擬軟體模擬X、Y及Z軸之靈敏度分別為128.7mV/g、135.6mV/g及104.5mV/g。電路上藉由分頻多工技術，利用單套電路完成多軸訊號之同時輸出。此分頻讀出電路操作範圍為9g，而三軸共用一套電路並共享最大電路輸出擺幅。當三軸同時產生正或負加速度訊號時，單軸最大操作範圍即為3g。

This thesis presents a capacitive three-axis accelerometer with frequency division multiplexing readout circuit fabricated in 0.18m CMOS MEMS process. The ladder electrode design proposed in this work is derived from multi-metal layers which are available in CMOS process and it provides a way to realize small area three axis accelerometer without wet-etching process. The accelerometer area is 0.453mm^2. The sensing system combines a multiplexing readout circuit. The system power dissipation is 0.5583mW. The MEMS structure behavior parameters can be simulated in Coventor, which is simulation software for MEMS, and create a equivalent model simulating with CMOS circuit in Cadence SpectreRF. The sensitivity of x, y and z axis are 128.7mV/g、135.6mV/g and 104.5mV/g respectively. By applying the chopper stabilization theorem, three axis signals can be processing simultaneously after the signals are shifted to their corresponding frequency bands. The output refer noise of x, y and z axis are 9.84 V/Hz-1/2, 8.36 V/Hz-1/2 and 7.44 V/Hz-1/2 respectively. The system sensing range is 9g which is shared by three axis acceleration signals.