非平面型三閘極鍺金氧半場效電晶體整合於矽平台

Abstract

半導體產業在過去的數十年中爆炸性成長，關鍵為金氧半場效電晶體的尺寸能夠持續微縮以致於增強元件特性，此被歸因於成熟的矽互補式金氧半場效電晶體技術。但是當電晶體的通道長度微縮至次10奈米的區域，電晶體元件的驅動電流難以提升及漏電流快速增加的問題限制此產業往後的發展，所以我們勢必找尋新的材料並改變元件結構才能使得元件特性能持續提升。為了能實現高性能及低功耗，非平面型三閘極結構擁有極佳的鍺通道控制能力因此俱備元件尺寸持續微縮能力，故此結構對於未來世代的演進是非常具有吸引力的。

此篇論文的第一部分，我們利用超高真空化學氣相沉積(UHVCVD)系統搭配沉積後退火(PDA)技術將單晶鍺全面性(blanket)磊晶於矽基板上，接著利用垂直式高台結構(mesa)並搭配二氧化鍺表面鈍化層(passivation)及三氧化二鋁隔絕層(isolation)製作出p+-Ge/n-Si和n+-Ge/p-Si異質接面二極體。這兩個二極體元件擁有非常高的電流開關比及低漏電流特性，其p+-Ge/n-Si和n+-Ge/p-Si分別有著 >107 和 >106的電流開關比。其p+-Ge/n-Si擁有極低的漏電流約 <10 μA/cm2即便使用不同的佈值能量10~40 keV；而對於n+-Ge/p-Si而言則有約20 μA/cm2的漏電流，使用20~50 keV的佈值能量，兩者皆於逆向偏壓VR= 1 V的條件下量測。然而，於順向偏壓VF = 1 V的量測條件下，其驅動電流分別約為120 A/cm2和50 A/cm2。

第二部分，我們接著研究鍺P通道和N通道基體連接(body-tied)三閘極(tri-gate)場效電晶體搭配高介電常數材料/金屬閘極堆疊並藉由上而下(top-down)的方法製作於矽基板上，而且此方式完全相容於矽標準製程。此P通道和N通道電晶體分別利用p+-Ge/n-Si和n+-Ge/p-Si異質接面高台結構做為電晶體元件的源極和汲極。除此之外，我們使用的高介電常數材料/金屬閘極堆疊在定電場應力量測下(constant field stressing)也展現了傑出的可靠度(reliability)特性。此基體連接三閘極鍺通道多重鰭型電晶體元件，P型通道長度為150 nm而N型通道長度為110 nm，鰭寬皆約為40 nm，在VG= 2 V的量測條件下分別擁有174 μA/μm和102 μA/μm的驅動電流。難能可貴的是，此實驗是第一個展示基體連接三閘極多重鰭型鍺通道場效電晶體。此外，我們也探討Ω型閘極於[010]通道傳導方向的N型金氧半場效電晶體，並展示其對抗短通道效應的能力即使將此元件的通道長度降至80 nm的情況下。電性方面，臨界擺幅(subthreshold swing)為136 mV/dec，汲極引致能障下降為56 mV/V，而且顯示約為2×105的元件開關切換比。

第三部分，我們第一次展示基體連接三閘極鍺通道無接面式(junctionless) P通道和N通道場效電晶體，並搭配鎳鍺(NiGe)合金作為源極/汲極材料。我們將鰭寬縮減至15~20 nm，其無接面式N通道元件比傳統的反轉式(inversion-mode)電晶體顯示出更佳的電特性。而且，我們也驗證了無接面式元件有著極佳的開關切換比及很好的抑制短通道效應能力。其多重鰭型無接面式N通道電晶體顯示出臨界擺幅為127 mV/dec，汲極引致能障下降為67 mV/V，且開關切換比約為2×105 (汲極電流)和107 (源極電流)於通道長度為150 nm情況下；元件漏電流為50 pA/μm於VDS = 0.1 V的量測條件下。另一方面，我們也證明了利用臨場(In-Situ)高摻雜技術可以大幅改善多重鰭型無接面式P通道電晶體的特性，如：臨界擺幅為203 mV/dec，汲極引致能障下降為220 mV/V，且開關切換比約為6.4×104 (汲極電流)和6×105 (源極電流)於元件通道長度為120 nm時。

第四部分，我們是第一位由實驗驗證了由GexSi1-x源極/汲極應力源(S/D stressor)的施加來改善三閘極N型鍺通道場效電晶體的電流特性，GexSi1-x應力源是藉由選擇性磊晶成長(selective epitaxial growth)的方式回填源極/汲極被蝕刻後的凹處。擁有Ge0.94Si0.06應力源的三閘極N型元件顯示出在通道長度為次100 nm的範圍其規格化後的峰值轉導值(peak gm)約為無應力源的元件的兩倍，並且此帶有應力的N型元件擁有出色的開關切換比約為105和不錯的臨界擺幅特性。更重要的是，在驅動電壓為1.5 V和VDS = 0.1 V的量測條件下帶有應力的元件比無應力的元件其源極電流約有2.2倍的增加。我們在源極/汲極區引入的Ge0.94Si0.06應力源除了電子遷移率(mobility)的增加外，也可以減輕費米能接釘札效應(Fermi-level pinning)，並且使源極/汲極的接觸電阻(contact resistance)有著27 %的改善。

最後一部分，我們也研究了高效能且低漏電的鍺長通道P型和N型蕭特基場效電晶體並以鎳鍺合金為源極/汲極。NiGe/n-Ge和NiGe/p-Ge蕭特基接面在V = 1 V的量測條件下其順偏/逆偏電流比分別約為105和2×104。P通道和N通道電晶體兩者的電性方面亦也顯示出相對高的開關切換比和不錯的臨界擺幅特性，在VGS-VT = 0.8 V和VDS = 1 V的量測條件下，分別有著約9 μA/μm和4 μA/μm的驅動電流，並且，P型和N型蕭特基場效電晶體的源極/汲極串聯電阻也分別比傳統p/n接面的元件有約22 %和43 %的改善。此外，我們也提出了藉由鉑添加於鎳鍺合金為源極/汲極而達到高效能的鍺長通道P型蕭特基場效電晶體。此外，鉑的引入不僅增加了製程溫度容忍度也達到更好的熱穩定性。NiGe:Pt/n-Ge蕭特基接面因有0.58電子伏特的等效電子能障高、理想因子為1.06並且串聯阻抗為11.1歐姆，使得此接面有接近於105的電流開關比。P通道電晶體顯示出極低的源極/汲極串聯電阻25 k歐姆/μm且有著極高的輸出電流27 μA/μm。與鎳鍺合金及鉑鍺合金的蕭特基場效電晶體比較後，引入少量鉑於鎳鍺合金中的電晶體其有著最好的汲極電流以及轉導特性。

In the past decade, a continuous scaling of MOSFETs dimensions to boost device performance it could be attributed to the well developed Si CMOS technology, which lead to explosive growth in the semiconductor business. As the transistor channel length shrink soon down to the sub-10 nm regime, the driving current and off-state leakage current have become limited and the innovation in materials and device structures will be needed for keeping performance enhancement. In order to realize high performance and low standby power consumption, non-planar tri-gate architecture with a Ge channel is a powerful and probable candidate for future generation owing to the excellent electrostatic control and hence channel length scalability.

In the first part of this dissertation, we introduced a heteroepitaxial growth of blanket Ge directly on Si substrate as starting material via ultra high vacuum chemical vapor deposition (UHVCVD) system and post deposition annealing (PDA). We demonstrated p+-Ge/n-Si and n+-Ge/p-Si heterojunction diodes from which with a GeO2 passivation and an Al2O3 isolation using the mesa structure, the characteristics of both diodes with a very high on/off current ratio and very low leakage current was achieved. The current ratio of p+-Ge/n-Si and n+-Ge/p-Si heterojunction was >107 and >106, respectively. The off current density was extremely low at <10 μA/cm2 for the p+-Ge/n-Si formed with different implantation energies of 10~40 keV and ~20 μA/cm2 for the n+-Ge/p-Si with different implantation energies of 20~50 keV at a reverse bias of VR= 1 V, respectively. High on current density ~120 A/cm2 for p+-Ge/n-Si and ~50 A/cm2 for n+-Ge/p-Si heterojunction at a forward bias VF = 1 V were presented.

In the second part, we then fabricated body-tied Ge P-channel and N-channel field effect transistors with tri-gate structure directly on a Si substrate with a high-κ/metal gate stack using a top-down approach and this scheme was fully compatible with Si standard processing. Both P-channel and N-channel transistors were formed by a mesa structure using these p+-Ge/n-Si and n+-Ge/p-Si heterojunctions. In addition, the high-κ/metal gate stack also shows excellent reliability under constant field stressing. The body-tied Ge multi-fin tri-gate FET with a fin width (WFin) was of ~40 nm and the channel length (LChannel) was 150 nm for PMOSFET and of 110 nm for NMOSFET, exhibiting a driving current of 174 μA/μm at VG = -2 V and 102 μA/μm at VG = 2 V, respectively. This is the first experimental demonstration of a body-tied Ge channel multi-fin tri-gate MOSFET. Moreover, we reported Ge N-channel Omega-gate (Ω-gate) MOSFET with [010] channel direction and providing immunity against short channel effect even channel length down to 80 nm. The electrical characteristics with subthreshold swing (S.S.) of 136 mV/dec, drain induced barrier lowering (DIBL) of 56 mV/V, and the ION/IOFF ratio 2×105 were demonstrated.

In the third part, we firstly demonstrate body-tied Ge tri-gate junctionless (JL) P- and N-MOSFETs with NiGe Source/Drain (S/D). Our tri-gate JL NMOSFET exhibits higher performance than conventional inversion-mode (IM) transistor through trimming down Ge fin width to 15~20 nm. We also show that JL devices had excellent ION/IOFF ratio and good SCE control on the channel potential. Furthermore, multi-fin JL NMOSFET depicted a S.S. of 127 mV/dec and DIBL of 67 mV/V at LChannel = 150 nm. The ION/IOFF ratio was ~2×105 (ID) and ~107 (IS). Off-state leakage current was of 50 pA/μm at VDS = 0.1 V. In-situ highly doped (ISHD) technique could significantly improve the characteristics of multi-fin JL PMOSFET. S.S. of 203 mV/dec, DIBL of 220 mV/V, and ION/IOFF ratio were ~6.4×104 (ID) and ~6×105 (IS) with LChannel = 120 nm.

In the fourth part, for the first time, we investigate the uniaxial tensile strained Ge tri-gate NMOSFETs with GexSi1-x S/D stressors for current improvement. The GexSi1-x S/D stressor was formed through selective epitaxial growth (SEG) after Ge recession. The tri-gate NMOSFET with Ge0.94Si0.06 stressor exhibits ~2× enhancement in the normalized peak gm over that without stressor when LChannel down to sub-100 nm. The strained NMOSFET showed excellent ION/IOFF ratio of ~105 and good subthreshold swing; mostly important, its drain current was significantly improved by ~2.2× as compared to that of the unstrained device at the overdrive of 1.5 V and VDS = 0.1 V. In addition to the enhancement in mobility, we introduce a Ge0.94Si0.06 stressor which can alleviate the Fermi-level pinning and in turn lead to a 27% reduction in S/D contact resistance.

Finally, we studied Ge P- and N-channel MOSFETs (long channel device) with NiGe Schottky S/D with high performance and low leakage current. The forward/reverse current ratio of the NiGe/n-Ge and NiGe/p-Ge Schottky junctions were ~105 and ~2×104 at V = 1 V, respectively. Both P- and N-channel MOSFETs show sufficiently high ION/IOFF ratio and good subthreshold swing. High driving currents of ~9 μA/μm and ~4 μA/μm at VGS-VT = 0.8 V and VDS = 1 V were obtained, respectively, for P- and N-MOSFETs. Besides, S/D series resistance of the Schottky P- and N-MOSFET was reduced by ~22 % and ~43 % as compared to that of the transistors with conventional p/n junctions. In addition, we also presented a high performance Ge P-channel Schottky MOSFET with a nickel germanide S/D fabricated by platinum incorporation. Platinum atoms were introduced into NiGe alloy to increase process window and thermal stability. The effective electron barrier height of 0.58 eV, ideality factor of 1.06, and series resistance of 11.1 ohm brought about a high NiGe:Pt/n-Ge junction current ratio of ~105. The PMOSFET depicted a low S/D resistance of 25 k×µm, and a remarkable high output current of 27 μA/μm. As compared to the NiGe and PtGe Schottky PMOSFETs, the NiGe:Pt Schottky PMOSFET does exhibit more superior drain current and peak transconductance.