具備源級跟隨PMOS讀取和位元線降壓電路的28奈米36Kb高速6T靜態隨機存取記憶體

Abstract

靜態隨機存取記憶體因為具有高速和高效能的特性,因此被廣泛地運用在系統晶片中。由於面積考量,傳統6T靜態隨機存取記憶體是現今的主流。許多靜態隨機存取記憶體的設計是採用傳統6T記憶胞 並搭配上一些輔助電路來提升效能。 並搭配上一些輔助電路來提升效能。 本論文提出一個具備源級跟隨PMOS讀取和位元線降壓電路的28奈米製程36Kb高速6T靜態隨機存取記憶體。在28nm時其PMOS相對而言較在其他製程有較強之推動能力,所以我們使用源級跟隨PMOS用來連接區域位元線和全域位元線。此記憶體之目標為高速,故為了進一步降低區域位元線和全域位元線的延遲時間,我們提出一個新的位元線降壓電路來降低區域位元線的電壓準位。設計晶片是透過台積電28HKMG奈米製程下線。在FF,溫度為125度C,電壓為1.08V時,該晶片的讀取時間為113微微秒;動態功率為38.4微瓦;待機功率為10.6微瓦;面積為16291微米平方。和現今靜體隨機存取記憶體編譯器的高速設計相比,讀取延遲時間少了19%;動態功率多了32%;待機功率少了40%;面積多了6.9%。

Static Random Access Memory (SRAM) has been widely used in the System on Chip (SOC) design because of its high operating speed and high performance. Traditional 6T SRAM bitcell becomes the mainstream due to its small area. Many SRAM designs adopt traditional 6T SRAM bitcell and uses some assistant circuits to improve the performance. In this paper, we presents 36Kb high speed 6T SRAM with source follower PMOS Read and Bit-Line Under-Drive. Because the driving ability of PMOS in 28nm technology is better than the other technology nodes, we use a source follower PMOS to connect Local Bit-Line (LBL) and Global Bit-Line (GBL). This SRAM targets at high speed, so we propose a new Bit-Line Under-Drive circuit to lower the voltage level of LBL to further reduce the propagation delay time of LBL and GBL. The SRAM test chip was fabricated in TSMC 28nm HKMG CMOS technology. At FF, 125°C, 1.08V, the access time is 113ps; the dynamic power is 38.4mW; the stand-by power is 10.6mW; the area is 16291 µm2. Compared with high speed circuit design in current SRAM compiler, the access time is 19% less; the dynamic power is 32% more; the stand-by power is 40% less; the area is 6.9% larger.