模型降階法在大量輸入輸出電路下之效能的改善

Abstract

模型降階法可簡化數學模型，提供更小維度的矩陣以利於計算並降低模擬所需時間。然而，此方法應用於許多輸入輸出埠的電路時，因為需要花更多時間計算，以及矩陣無法有效縮減，導致其效能嚴重下降。為了能讓此法更適用於許多輸入輸出埠的電路上，本篇結合叢集式(clustering)模型降階法與分治式(divide-and-conquer)降階法來達到效率。藉由將許多輸入輸出埠的電路拆解為單一輸入的電路，模型降階法可快速在各個單一輸入的電路上計算。此外，分治式降階法可避免直接對原電路進行計算，進而降低運算時間。由於叢集式與分治式的方法皆能達到矩量匹配的性質，當欲匹配矩量數目小於二時，本方法可達到與單一使用叢集式降階時近乎相同的準確性。實驗結果顯示本方法在速度上優於單一使用叢集式降階法，並且不失太多準確度。

Model order reduction (MOR) can reduce a model to help accelerate simulation. However, circuits with many terminals that are MIMO systems will degrade the performance of MOR such that the size cannot be reduced. Moreover, it takes much more time to reduce this type of circuits. To reduce these circuits more efficiently, this work combines clustering MOR with divide-and-conquer strategy. By splitting an MIMO system into several SISO systems, MOR can be executed on respective SISO systems to achieve efficiency. Besides, that divide-and-conquer strategy avoids performing reduction on entire circuit can accelerate clustering MOR method. With the moment matching properties that clustering and divide-and-conquer methods provide, the proposed method can achieve nearly the same accuracy compared to clustering method executed alone when the number of matched moments is not greater than two. The experimental results show speed-ups of proposed method over clustering method without losing much accuracy.