高性能之二進位式數位類比轉換器

Abstract

在今天的系統單晶片或無線通訊系統中，面積與功率消耗是第一重要的性能指標。對數位類比轉換器(DAC)而言，二進位數位類比轉換器的架構因具有高速，小面積和低功率的優點，所以被廣泛應用在無線通訊、影像和系統單晶片的數位類比轉換器單元。因此本論文研究聚焦在高性能的二進位電流式數位類比轉換器，並以電路技巧來改善一般二進位數位類比轉換器的缺點。 研究內容的第一個部分，提出一個十位元的高速、低突波的純二進位電流式數位類比轉換器。本研究使用了一個可變延遲電路來減少不同位元之間的時序誤差，進而降低暫態突波能量和提高無失真動態範圍。由實驗結果證實在主碼轉換時，透過可變延遲電路的幫助，取樣率是250MS/s條件下，暫態突波能量由132pVsec (無可變延遲電路)降低為1.36pVsec (有可變延遲電路)。 我們也比較了有無使用可變延遲電路的無失真動態範圍量測結果，其差異性可達到10dB以上。此數位類比轉換器由標準的CMOS 0.18μm製程來實現，在單一電壓源1.8V下，功率消耗19mW。 研究內容的第二部分，提出另一種降低不同位元之間的時序誤差的方法。我們使用了動態電容的計算方法來更精準地估測電流開關的輸入電容，然後再針對不同位元間的輸入電容值來做補償。除此之外，為了提升高頻訊號時的無失真動態範圍，在電路佈局時，我們將電流源和電流開關整合成一個單元。本次實驗實現了一個十位元400MS/s的純二進位電流式數位類比轉換器。由實驗結果證實，在主碼轉換時，暫態突波能量的量測值小於1pVsec。不論是在速度或突波能量上，都比第一次設計更好。此數位類比轉換器晶片在單一電壓源1.8V下，功率消耗20.7mW，由標準的TSMC 1P6M 0.18μm CMOS製程來實現。 最後，由於電流式數位類比轉換器的面積主要是由電流源的面積來主導，因此我們設計新的電流源電路架構來降低晶片面積，而且不需要使用數位校正電路。在論文的第三部份，我們提出了一個12位元二進位的雙參考電流源之電流式數位類比轉換器的新架構。一般12位元電流式數位類比轉換器需要4096個電流源陣列電晶體，而在新架構中，我們只需要128個電流源陣列電晶體，並且我們所設計的雙參考電流源產生電路的晶片面積不大。整個12位元的晶片面積是 0.36mm2, 接近一個10位元數位類比轉換器的大小。除此之外，其單一電流源電晶體的輸出阻抗也可降低為原來的三十二分之一。完整的數位類比轉換器晶片在單一電壓源1.8V下消耗37.8mW。

Nowadays, area and power are the most important performance metrics in SOC or wireless communication systems. For the digital-to-analog converters (DACs), as binary-weighed DACs have the advantages of high speed, small area, and low power, they are widely used in many wireless communication systems, video systems, and SOC applications. Therefore, this research focuses on the high performance binary-weighed current-steering DACs, and utilizes circuit techniques to improve the drawbacks of binary-weighted DACs. In the first part of this research, a 10-bit high-speed and low-glitch pure binary-weighted current-steering DAC was proposed. The proposed converter uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce glitch energy and improve spurious-free dynamic range (SFDR). Experimental results validate the glitch reduction from using variable-delay buffers in the input data path. The glitch energy during major code transition is reduced from 132pVsec (without variable-delay buffers) to 1.36pVsec (with variable-delay buffers) under 250MS/s clock rate. And the improvement in the SFDR of the DAC is over 10dB by using variable-delay buffers. The DAC implemented in a standard 0.18um CMOS technology dissipates 19mW from a single 1.8V power supply. For the second part of this research, , the other approach of reducing timing-skew among different bits was proposed. The calculation method of dynamic capacitance was used to estimate the input capacitance of the current switches more precisely, and capacitance compensation was made for the input capacitance among different bits. In addition, to increase dynamic SFDR at high signal frequency, the current switches and current source transistors are combined as a unit cell in the layout. This research implements a 10-bit 400MS/s pure binary-weighted current-steering DAC. Experimental results demonstrate the glitch energy is smaller than 1pVsec during major code transition. Either glitch or spurious-free dynamic range was proven to be better than the first part of this research. The DAC implemented in a standard TSMC 1P6M 0.18um CMOS technology dissipates 20.7mW from a single 1.8V power supply. Finally, as the area of a current-steering DAC is dominated by the size of current source arrays, the new architecture of current source arrays was designed to reduce the chip area without digital calibration. The third part of this dissertation presents a new architecture of 12-bit binary-weighted current-steering DAC with dual reference currents. Instead of 4096 unit current cells required for conventional 12-bit DAC, the proposed design uses only 192 unit current sources, and the silicon area of the generation circuit of two reference currents is very compact as well. The core areas of the 12-bit DAC is only 0.36mm2, almost the same as that of a 10-bit DAC. Besides, the output impedance of the unit current-source transistor can be reduced to 1/32 that of the conventional DAC. The entire DAC, fabricated by 0.18μm CMOS process, dissipates 37.8mW from a single 1.8V power supply.