高壓元件LDMOS之特性分析與靜電放電防護設計

Abstract

近年來，高功率積體電路興起並有廣泛的應用，而具有平面結構的LDMOS（橫向雙擴散之金氧半場效電晶體）有高度整合性，於焉成為主要的驅動元件。首先，我們將探討橫向雙擴散之金氧半場效電晶體的特性，包括基本電流-電壓特性、崩潰機制、以及與崩潰機制有關的重要製程參數。根據以上的討論，我們提出一些方法來有效抑制克爾克效應(Kirk Effect)的發生得以提升橫向雙擴散之金氧半場效電晶體的安求全工作區間(Safe-Operating-Area)。該佈局成效已於一0.8 微米40V高壓製程中獲得實際驗證。 論文中另一個部分為探討橫向雙擴散之金氧半場效電晶體的靜電防護設計，橫向雙擴散之金氧半場效電晶體普遍具有不佳的靜電放電防護能力。在此論文中，我們找出造成橫向雙擴散之金氧半場效電晶體靜電放電防護能力不佳的主要的兩個原因，藉由消除這兩個根本的原因，一新的結構在章節三和四中被提出，由實驗結果證實此結構能有效的提升其靜電放電的能力。該佈局成效已於高功率0.25 微米高壓製程中獲得實際驗證。

High voltage integrated circuits are emerging in a wide variety of application nowadays. LDMOS (Lateral Double-Diffused MOSFET) is usually the driver component in these circuits, thanks to its planar structure. First, we will engage in the characteristics of LDMOS, including the I-V curve discussion, the breakdown mechanism, and some of the key specific parameters related to breakdown voltage. According to the above discussion, we propose some advices to optimize the Safe-Operating-Area (SOA) of LDMOS by minimizing the Kirk effect. It is verified in 0.8 m 40V HV technology. Another part of our study is the investigation of ESD protection designs of LDMOS. The LDMOS devices in HV technologies are known to have poor ESD robustness. In this thesis, the root causes of the high voltage (HV) LDMOS failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to improve the ESD robustness by eliminating the root causes in Chapter 3 and 4. The proposed layout on high-voltage LDMOS has been successfully verified in a 0.25 m 20V BCD process without using additional process modification. Experimental results have shown significantly improved ESD robustness of LDMOS.