2.2mW 5GHz 全數位鎖相迴路用於在類比多音收發器

Abstract

Nowadays, the all-digital PLL is a vital block of high speed serial link applications. The proposed low power and high speed ADPLL has been implemented and integrated with analog multi-tone (AMT) transceiver. The ADPLL design specification is based on the whole integrated system requirements. One of the most important design requirement is low power constraint for 5 GHz quadrature output signal. In order to achieve the low power requirement, a low reference clock frequency has been used in the ADPLL and DCO with less varactor capacitance is also implemented. One other design constraint is a spur energy performance, which is caused from the fixed period of the reference clock frequency. The unwanted spur power will be appeared in the ADPLL output spectrum. Thus, it degrades the system application performance. A random-sampling technique has been proposed to eliminate the reference spur in the ADPLL output spectrum. This technique randomizes the phase of the reference clock without change of the clock period. Besides, jitter performance is also important design parameter of the ADPLL system. The proposed design has a better jitter performance due to the use of equally sized unary varactor arrays in the DCO. The NMOS transistor is designed as a varactor instead of using NMOS varactor from TSMC standard cells. That is because of the limitation of TSMC Varactors in both frequency resolution performance and the power consumption. The proposed ADPLL is based on bang-bang architecture. It has the ability to adjust the loop parameters during the locking modes to achieve better performance in terms of jitter and spur performance. Besides, the digitally controller oscillator (DCO) is a multi-phase differential ring oscillator. It uses a multi-band technique to compensate the voltage and temperature variations. Also, the tuning method of the DCO is based on the use of unary varactor arrays as a loading capacitance to achieve better linearity. The ADPLL has been designed by using of logic cells from standard cell library. The ADPLL design can be divided into two parts. One part is the digital controller which is implemented by a cell-based design flow. The other part is the DCO, which is implemented by a custom design flow. The ADPLL chip is implemented in TSMC 40nm LVT CMOS process technology. It provides 4 multi-phase 5GHz output clock signals and two 2.5 GHz clock signals. The output phases have (∼ 50%) duty cycle. The DCO tuning range is 736 MHz. The multi-band technique can compensate the VT variation in a range of 0:9V ± 3:33% and 0?C ∼ 85?C. The rms and peak-to-peak cycle jitter are 245.96 fs and 3.649 ps ,respectively. The reference spur level is -59 dBc lower than the carrier. The core area of the digital controller and DCO are 0:0225 mm2 and 0:001656 mm2, respectively. The ADPLL power consumption is 2.2 mW from 0.9V supply voltage.

Nowadays, the all-digital PLL is a vital block of high speed serial link applications. The proposed low power and high speed ADPLL has been implemented and integrated with analog multi-tone (AMT) transceiver. The ADPLL design specification is based on the whole integrated system requirements. One of the most important design requirement is low power constraint for 5 GHz quadrature output signal. In order to achieve the low power requirement, a low reference clock frequency has been used in the ADPLL and DCO with less varactor capacitance is also implemented. One other design constraint is a spur energy performance, which is caused from the fixed period of the reference clock frequency. The unwanted spur power will be appeared in the ADPLL output spectrum. Thus, it degrades the system application performance. A random-sampling technique has been proposed to eliminate the reference spur in the ADPLL output spectrum. This technique randomizes the phase of the reference clock without change of the clock period. Besides, jitter performance is also important design parameter of the ADPLL system. The proposed design has a better jitter performance due to the use of equally sized unary varactor arrays in the DCO. The NMOS transistor is designed as a varactor instead of using NMOS varactor from TSMC standard cells. That is because of the limitation of TSMC Varactors in both frequency resolution performance and the power consumption. The proposed ADPLL is based on bang-bang architecture. It has the ability to adjust the loop parameters during the locking modes to achieve better performance in terms of jitter and spur performance. Besides, the digitally controller oscillator (DCO) is a multi-phase differential ring oscillator. It uses a multi-band technique to compensate the voltage and temperature variations. Also, the tuning method of the DCO is based on the use of unary varactor arrays as a loading capacitance to achieve better linearity. The ADPLL has been designed by using of logic cells from standard cell library. The ADPLL design can be divided into two parts. One part is the digital controller which is implemented by a cell-based design flow. The other part is the DCO, which is implemented by a custom design flow. The ADPLL chip is implemented in TSMC 40nm LVT CMOS process technology. It provides 4 multi-phase 5GHz output clock signals and two 2.5 GHz clock signals. The output phases have (∼ 50%) duty cycle. The DCO tuning range is 736 MHz. The multi-band technique can compensate the VT variation in a range of 0:9V ± 3:33% and 0?C ∼ 85?C. The rms and peak-to-peak cycle jitter are 245.96 fs and 3.649 ps ,respectively. The reference spur level is -59 dBc lower than the carrier. The core area of the digital controller and DCO are 0:0225 mm2 and 0:001656 mm2, respectively. The ADPLL power consumption is 2.2 mW from 0.9V supply voltage.