雙介電層低功耗電阻式記憶體之設計與導通機制探討

Abstract

傳統非揮發性記憶體如FLASH 和SONOS 等快閃記憶體有著許多先天上難以克服的缺點，如隨機摻雜擾動（Random Dopant Fluctuation）、隨機電報雜訊（Random Telegraph Noise）和寫抹不匹配(Mismatch between Program and Erase)，穿隧氧化層厚度也阻礙了元件的微縮。為了解決這些的問題，電阻式記憶體近年來成為非揮發性記憶體的熱門主題，乃因其擁有高密度、低成本、結構簡單、製程容易及具有極佳的微縮特性等優點。至於電阻式記憶體的氧化物材料有很多選擇，像是三氧化二鋁、氧化鎳、二氧化鉿等。而在本論文中，吾人將製作以氮氧化鉿和三氧化二鋁為基底之電阻式記憶體並探討其特性。

首先，我們探討單、雙層介電層電阻式記憶體之間的差異，由轉態的特性可以觀察出雙介電層元件具有較佳的穩定性。而在退火方面，我們嘗試了三種不同的溫度，並從中選取出最適合的條件。除此之外，也探討不同氧化層厚度對於電阻式記憶體特性的影響。綜合上述三項實驗結果，我們成功地優化元件的表現，包含良好的耐久度(endurance)及資料保存(retention)特性。

其次，我們運用隨機電報雜訊分析，來了解路徑產生對記憶體的判讀產生的影響。藉由觀察隨機電報雜訊電流擾動的振幅趨勢，可以推測出軟性崩潰路徑(soft breakdown path)的分佈。並根據分析結果，從結構方面著手改良元件，使其能更符合低功耗操作之應用。除此之外，為達到記憶體高速操作之特性，我們運用極短的脈衝(pulse)來操作元件，並在此種操作方法之下得到良好的元件可靠度。

Charge-trapping memory devices (e.g., FLASH, SONOS etc.) have several inherent disadvantages that are difficult to overcome, such as random dopant fluctuation, random telegraph noise, and mismatch between program and erase. The thickness of tunnel oxide also restricts devices scaling. In order to solve these problems, Resistance-change Random Access Memory (RRAM) has recently received much more attention as a result of high-density, low-cost, simple structure (Metal-Insulator-Metal), easy fabrication, and excellent potential of scaling. As to the oxide materials, there are many choices such as Al2O3, NiO, HfO2, etc. In this thesis, we will prepare HfON/Al2O3-based RRAM and investigate device characteristics.

First, we make a comparison between single layer devices and bi-layer ones. The switching characteristics of bi-layer RRAM show better stability. As to the effect of annealing, three different temperatures will be used to anneal the prepared devices, and the most suitable condition of them is selected for our process. Besides, a series of tests have also been carried out to understand how the oxide thickness affects characteristics of RRAM. Taking experiment results as mentioned above into account, we successfully optimize device performances including good endurance up to 1,000 times and retention in 10,000 second.

Next, the RTN analysis will be used to examine the effects of soft breakdown paths in RRAM devices. By analyzing the trend of RTN current amplitude, the configuration of soft breakdown paths can be identified. Based on RTN analysis results, we improve device performances by changing the composition of dielectric layer and make it more acceptable for low power applications. Furthermore, pulse operation method is applied to replace DC sweep with a view to obtaining the high speed operation. The devices show good reliability for non-volatile memory applications by pulse operation.