高介電常數材料之低溫複晶矽快閃記憶體的研究

Abstract

在本論文中，我們提出在低溫複晶矽薄膜上製作非揮發性快閃記憶體。首先，改變不同高介電常數材料當作記憶體元件的電荷補陷層(Trapping layer)，在此我們所使用的高介電常數材料分別是二氧化鉿(HfO2)、鉿矽酸鹽(Hf-silicate)以及鋯矽酸鹽(Zr-silicate)，對快閃記憶體元件做特性及可靠度分析，我們可以發現我們所製作的低溫複晶矽薄膜快閃記憶體具有以下幾個特點：(1)三種不同的電荷補陷層製作出的記憶體元件，都具有記憶視窗大的特性；(2)在資料寫入/抹除(Program/Erase)的速度表現上，三種材料的記憶體元件都可以達到毫秒級以上的資料寫入/抹除速度；(3)在資料保存能力(Data retention)上的表現，三種材料的記憶體元件在室溫量測下，推測十年後的電荷保存能力都可以維持在70%以上，鉿矽酸鹽的記憶體元件甚至可以達到保存90%以上的電荷；(4)在元件耐久度(endurance)測試下，三種材料的記憶體元件經過資料反覆寫入/抹除十萬次，記憶視窗的大小都維持的很好，沒有因為反覆寫入/抹除而造成記憶視窗關閉的情形；(5)記憶體具有單一元件二位元(2bits/cell)操作特性。 本篇論文另外探討改變不同穿隧氧化層(Tunneling oxide)厚度對元件特性的影響，其中穿隧氧化層較厚的在資料保存能力上有較好的特性，然而兩種不同厚度的穿隧氧化層在資料寫入/抹除速度上分別不大，但是在抗閘極干擾(Gate disturbance)及抗汲極干擾(Drain disturbance)特性上，對低溫複晶矽薄膜快閃記憶體仍然是一個問題。我們將製作好的元件利用氨電漿(NH3 plasma)處理後，可以大幅改善元件在資料保存能力、抗閘極干擾及抗汲極干擾的特性，不過氨電漿修補介面懸鍵及複晶矽通道中的載子補獲態(Trap states)仍然有限，如果可以找到更好的方法排除介面懸鍵及複晶矽通道中的載子補獲態對元件造成的影響，未來低溫複晶矽快閃記憶體在應用上就能更有發展空間。

In this thesis, we proposed the fabrication of low temperature polycrystallize silicon thin film with nonvolatile flash memory as named the SONOS-type poly-Si-TFT memories. In addition, the different high-k materials of trapping layer were used in this experiment, including the HfO2, Hf-silicate and Zr-silicate. We also analyze the electrical properties and the reliability of the SONOS-type poly-Si-TFT memories. It was demonstrated that the fabricated memories exhibit good performance. First, the large memory window was shown in the device with three different trapping layers. Second, these samples would have the high program/erase speed (1ms/10ms). Third, all the three samples can be operated up to 108 s with only 30% charge loss for the data retention performance under room temperature operation. However, the data retention for the sample with Hf-silicate trapping layer can be operated up to 108 s with only 10% charge loss. Fourth, our devices also have long retention time (>106s for 20% charge loss) and negligible read/write disturbances. Fifth, the 2-bit operation has been successfully demonstrated in these devices with different trapping layers. We also discuss the electrical characteristics of SONOS-type poly-Si-TFT memories with different tunneling oxide thickness. The device with thicker tunneling oxide thickness would have better data retention performance than the sample with thinner tunneling oxide thickness. In addition, our device with thicker tunneling oxide thickness would have good program/erase speed as well as the device with thinner tunneling oxide thickness. However the gate and drain disturbance are still problems in low temperature poly-crystallize silicon thin film flash memories. After NH3 plasma treatment, the performances of data retention and disturbance would be improved for our SONOS-type poly-Si-TFT memories. This is because the hydrogen atoms of NH3 can terminate dangling bonds and replace the weak bonds in the grain boundaries and SiO2/poly-Si interface and thus reduce the trap states in the poly-Si channel. Thus, both the performance and reliability of poly-Si TFTs were also improved. As long as the drain and gate disturbance can be reduced, this TFT flash memories are very promising for the future flash memory application.