高介電材料於鍺基板及異質磊晶鍺元件於矽平台之研究

Abstract

本論文研究使用鍺(Ge)材料作為互補式場效電晶體(CMOS)之通道材料，研究內容包括閘極堆疊結構(gate stack)，異質磊晶(heteroepitaxy)鍺於矽基板，以及先進場效電晶體結構。 在閘極結構部分，我們使用三種不同閘極堆疊結構研究其電容之絕緣體與鍺介面特性及製作元件分析其特性。首先，為了改善介面特性，我們在高介電層與鍺基板間成長一層二氧化鍺(GeO2)薄膜。藉由此層熱成長二氧化鍺薄膜，可以有效降低介面能態密度(interface state density, Dit)，並且經過氮氣氫氣混合熱退火(forming gas annealing, FGA)後，更可以再度降低介面能態密度，而透過電導法(conductance method)以及費米能階效率(Fermi-level efficiency)萃取，在能隙中央的值約在5×1011 cm-2eV-1。透過 對 圖形的外插，可萃取出電子及電洞的捕捉截面積(capture cross section)，分別為2.7 – 4.2 × 10-16及7.8 – 9.6 × 10-16 cm2。藉由低溫量測，可以成功取得在能隙邊緣的介面能態密度，並有效抑制弱反轉效應(weak inversion reponse)。因此，可以得到三氧化二鋁/二氧化鍺(Al2O3/GeO2)閘極堆疊的介面能態密度為U型分布。經由成功製作高介電層於鍺基板上的經驗，我們成功使用此閘極堆疊搭配後閘極製程製作鍺p型場效電晶體。表面鈍化與無表面鈍化之電晶體在高電場區域之電洞遷移率分別為矽普遍曲線(Si universal curve)的1.7及1.3倍。經過氮氣氫氣混合熱退火後，由於有較低的接面逆偏電流以及較佳的介面特性，因此可以獲得較佳的開關比(on/off ratio, 3.3 order)及次臨界擺幅(subthreshold swing, S.S., 170 mV/dec)。 我們使用二氧化鉿/三氧化二鋁/氧化鍺(HfO2/Al2O3/GeOx)作為閘極堆疊來降低等效氧化層厚度(effective oxide thickness, EOT)。氧化鍺為藉由先成長三氧化二鋁於鍺基板再進行後氧化退火(post deposition oxidation, PDO)完成。在520度後氧化退火3分鐘並在氮氣環境下進行後沉積退火，由於具有較薄的氧化鍺薄膜並搭配具有較高介電系數的二氧化鉿，等效氧化層厚度可以降低至1.6奈米，藉由電導法萃取在能隙中央的介面能態密度約為1.5~5×1012 cm-2eV-1。透過X射線光電子能譜(X-ray photoelectron spectroscopy, XPS)分析，可以歸納出當有較厚的氧化鍺中間層以及較高的Ge3+峰值，可以得到較佳的介面品質。經過300度30分鐘之氮氣氫氣混合熱退火後，介面能態密度可以降低至1.1~2.5×1012 cm-2eV-1，而平帶電壓(flat band voltage)會正偏移，並且有較小的電容磁滯(C-V hysteresis)現象。我們使用此閘極堆疊結構並搭配後閘極製程完成鍺p型及n型場效電晶體，並探討氮氣氫氣混合熱退火對元件特性影響。與電容結果相同，在經過氮氣氫氣混合熱退火後，p型及n型電晶體之次臨界擺幅有效改善為165及151 mV/dec。雖然額外的熱退火造成串聯阻抗上升，但由於改善了接面特性並有效提升載子遷移率，因此驅動電流上升。然而，由於n型參雜容易在退火過程中向外擴散，並且有費米能階釘扎(Fermi-level pinning)現象，因此造成高阻抗及高蕭特基能障(Schottky barrier height)，使得n型電晶體的輸出特性大幅劣化。 接著，我們使用另一種高介電層材料，二氧化鋯(ZrO2)，在不加入中間層情況下直接成長於鍺基板。二氧化鋯沉積方式為使用電漿輔助原子層沉積系統，使用的前驅物為四(乙基甲基氨基)锆(TEMAZr)。我們針對成長及退火溫度對二氧化鋯電容之影響進行電性及物性分析。藉由電容的電性分析，在600度氮氣後退火條件下，等效氧化層厚度為1.33奈米，而介面能態密度在能隙中央約為5.4 × 1011~2 × 1012 cm-2eV-1。能帶彎曲效率(band bending efficiency)可以藉由準靜態電容(quasi-static C-V)量測搭配Berglund積分法獲得。透過X射線光電子能譜可以發現在原子層沉積過程，介面會形成一層超薄氧化鍺薄膜。我們使用二氧化鋯閘極堆疊搭配後閘極及前閘極製程完成兩種鍺p型及n型場效電晶體，並比較兩種製程的優缺點。使用後閘極製程p型及n型電晶體之次臨界擺幅分別為119.1 mV/dec及112.5 mV/dec，而使用前閘極製程分別為121.9 mV/dec及105.3 mV/dec。由於較多的熱預算會帶來較嚴重的參雜擴散，使用後閘極製程之電晶體具有較高的串聯阻抗。藉由比較高電場區域之載子遷移率以及穿透式電子顯微鏡(transmission electron microscopy, TEM)觀察，可以發現後閘極製程表面較為粗糙。藉由此實驗結果，我們認為使用二氧化鋯閘極氧化層搭配先閘極製程可以降低串聯阻抗並改善元件特性。 為了將鍺整合至矽基板平台，我們直接異質磊晶鍺於矽塊材基板並搭配高溫循環退火改善薄膜品質。藉由三次循環高溫退火，磊晶鍺薄膜之霍爾遷移率(Hall molity)可以有效從325 cm2/V-s改善至1332 cm2/V-s，而X光繞射能譜(X-ray diffraction, XRD)之半高寬可以從0.097度縮小為0.058度，貫穿式差排密度(threading dislocation)約為106~107cm-2。另外我們也選擇性異質磊晶鍺於具有奈米級圖形化之矽溝槽中。矽溝渠為使用標準淺溝槽隔離(shallow trench isolation, STI)製程所完成，最小的溝槽寬度僅有50奈米。在鍺薄膜中的貫穿式差排可以藉由高溫退火而滑移移動或消失於薄膜中。在較小的溝槽中，由於貫穿式差排滑移至氧化矽側壁距離很短，因此可以有效消除貫穿式差排。若在較寬的溝槽中，貫穿式差排有機率會合併形成無法移除的無滑動差排(sessile dislocation)。最後，藉由奈米電子束繞射(nano-beam diffraction)，可以觀察到由於經過多次高溫退火，磊晶鍺薄膜不具有應力存在。 基於製作閘極堆疊以及異質磊晶鍺於矽平台的經驗，我們整合鍺薄膜於絕緣上矽基板並製作鍺魚鰭式電晶體(FinFET)。直接異質磊晶鍺於高阻抗薄絕緣上矽基板可以提供鍺元件製作。絕緣上鍺基板結構可以有效抑制接面逆偏電流，因此可以得到較高開關比的汲極電流(~5 × 105, at VD = 0.1 V)。三閘極結構可以有效抑制鍺魚鰭式電晶體的短通道效應，而汲極導致位障降低(drain-induced-barrier-lowering，DIBL)以及臨界電壓(threshold voltage, VTH)飄移可以在通道長度為120奈米及鰭寬40奈米下仍分別維持在~110 mV/V及0.1 V。我們同時也製作多鰭式(multi-fin)魚鰭式電晶體，n型及p型電晶體皆具有超過104的開關比特性。此外，藉由氮氣氫氣混合熱退火也可以有效降低25%的次臨界擺幅。

In this dissertation, we have investigated the feasibility in using Ge as channel material of CMOS devices, including gate stacks, hetero-epitaxial Ge on Si substrate, and advanced device structure. Various high-κ gate stacks on Ge substrates have been demonstrated and studied by evaluating the interface quality of capacitors and device characteristics. Firstly, high-κ/Ge capacitors were performed with an ultra-thin GeO2 interfacial layer to improve the interface quality. The GeO2 layer ,which was grown by thermal oxidation, could effectively suppress the interface state density, and the Dit could be effectively reduced after forming gas annealing, with value about 5×1011 cm-2eV-1 near the midgap from either conductance or Fermi-level efficiency method. By extrapolation of versus , the determined σn and σp were about 2.7 – 4.2 × 10-16 and 7.8 – 9.6 × 10-16 cm2, respectively. By low temperature measurement, the Dit near band edge could be successfully extracted, and weak inversion response was also suppressed near midgap. Therefore, a normal U-shaped Dit distribution of Al2O3/GeO2 gate stack was revealed. With the experiences of integrating high-κ dielectric on the Ge substrate, Ge p-MOSFETs with the gate stack were successively fabricated by gate-last scheme. The high-field mobility of the MOSFETs with and without GeO2 passivation was 1.7 and 1.3 times higher than the Si universal curve, respectively. Also, better on/off ratio (3.3 orders) and subthreshold swing (170 mV/dec) were attained after FGA, resulted from lower reverse bias junction leakage and better interface quality. A gate stack with lower EOT, HfO2/Al2O3/GeOx, was subsequently demonstrated. A thin GeOx interfacial layer beneath an ALD-Al2O3 layer was performed by using post deposition oxidation method. Accompanying with HfO2 dielectric and relatively thin GeOx passivation layer, the EOT value was scaled down to 1.6 nm for the sample with PDO at 520 °C for 3 min and PDA in N2 ambient, and the Dit extracted from conductance method was about 1.5~5×1012 cm-2eV-1 near midgap. Through XPS analysis, less interface state density was due to that the thicker GeOx interfacial layer and larger Ge3+ peak improved the interface quality. Interface state density was shown to be reduced to 1.1~2.5×1012 cm-2eV-1 after forming gas annealing at 300 °C for 30 min, and positive VFB shift and lower C-V hysteresis was also obtained after FGA. Ge MOSFETs with HfO2/Al2O3/GeOx gate stack were fabricated by the gate-last scheme. The effect of forming gas annealing on the device characteristics was discussed. Consistent with the results of MOSCaps, the subthreshold swing was improved to 165 and 151 mV/dec for p-FET and n-FET after FGA, respectively. Even though the series resistance for both devices was increased, the driving current was improved because of the improvement in the interfacial quality and resultant higher carrier mobility. However, due to the fact that the n-type dopants easily out-diffused during thermal annealing and Fermi-level pinning, high series resistance and Schottky barrier height caused degradation in output characteristic of n-MOSFET. Subsequently, an alternative high-κ material, ZrO2, was carried out to study the gate stack without any intentional interfacial layer on the Ge substrate. The ZrO2 thin film was deposited by plasma-enhanced ALD with TEMAZr precursor. The effect of growth and PDA temperature on MOSCaps was electrically and physically analyzed. Even through the electrical analysis of MOSCaps, the EOT and Dit of ZrO2/Ge gate stack with PDA at 600 °C in N2 ambient were 1.33 nm and 5.4 × 1011~2 × 1012 cm-2eV-1 near midgap, respectively. By using quasi-static C-V curve and Berglund integral, the band bending efficiency could be estimated from the surface potential. XPS spectra also showed that an ultra-thin GeOx layer was formed during ALD deposition. The Ge p-MOSFETs and n-MOSFETs with ZrO2 gate stack were performed by both gate-last and gate-first processes to compare the pros and cons of two different schemes. The subthreshold swing using gate-last process was ~119.1 mV/dec for p-MOSFET and ~112.5 mV/dec for n-MOSFET, while using gate-first process was ~121.9 mV/dec for p-MOSFET and ~105.3 mV/dec for n-MOSFET. Using gate-last scheme revealed larger series resistance for both p- and n-MOSFET, indicating dopants out-diffusion was much severe due to more thermal budget. The high-field hole mobility showed that the surface roughness was rougher for gate-last MOSFET, and cross-sectional TEM images also confirmed this inference. According to our demonstration, we consider ZrO2 was a stable material on Ge and using gate-first scheme could effectively reduce series resistance and in turn increase device performance. In order to integrate Ge on Si platform, we investigated hetero-epitaxial Ge on blanket substrate accompanying with high temperature cyclic annealing. By using in-situ annealing process, the epitaxial Ge film with 3-cycle high temperature annealing demonstrated that the Hall mobility increased from 325 to 1332 cm2/V-s, and the values of the full width at half maximum decreased from 0.097 to 0.058 degree. The dislocation density of epitaxial Ge film was around 106 ~ 107 cm-2. The selective growth of germanium into nanoscale trenches on silicon substrates was also demonstrated. The nanoscale trenches were fabricated using the state-of-the-art shallow trench isolation technique, and the smallest width was only 50 nm. Threading dislocations in Ge film could glide and be annihilated by high temperature annealing. In small trenches, threading dislocations could be readily removed because their gliding distance to the SiO2 sidewalls was short. In contrast, threading dislocations might combine and form sessile threading dislocations in larger pattern size. Nano-beam diffraction analysis showed that the epitaxial Ge film within the trenches was fully relaxed after cyclic thermal annealing. Finally, based on the previous experiences of fabricating gate stacks and hetero-epitaxy, integrating Ge thin film on silicon-on-insulator substrate and performing Ge fin field-effect-transistors (FinFETs) have been demonstrated. Directly grown Ge film on high resistivity thin SOI substrate provided a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high Ion/Ioff ratio (~5 × 105, at VD = 0.1 V) of drain current has been achieved. Tri-gate structure provided better short channel control abilities for the Ge FinFETs, and the drain-induced-barrier-lowering (DIBL) and threshold voltage (VTH) shift could be maintained at the level of ~110 mV/V and ~0.1 V, respectively, for Ge n-channel FinFET with Lchannel = 120 nm and WFin = 40 nm. Multi-fin Ge FinFET with Lchannel = 170 nm and WFin = 50 nm was also illustrated. Both N- and P-FinFETs possess high Ion/Ioff ratio over 104. Besides, the sub-threshold swing could be reduced about 25% after forming gas annealing.